Analog Integrated Circuits (Jieh Tsorng Wu)

2 2 power conversion eciency c output stages pl

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Unformatted text preview: resistor R2 . • Reference: Song, et al., JSSC 12/83, pp. 634–643. Voltage and Current References 9-27 Analog ICs; Jieh-Tsorng Wu Band-Gap Reference Output Issues Reference Generator VO C Reference Generator L VO RG V’ O RG RG Reference Generator VO VO R RG RG R Voltage and Current References 9-28 Analog ICs; Jieh-Tsorng Wu Band-Gap Reference Output Issues • Feedback is employed in the reference generator. Loop stability must be ensured. • The stability can be tested by observing the output step response. • Capacitive loading at the output of reference generator has to be either extremely large (i.e., off-chip capacitors, undesirable because of extra pin, lead inductance, ...) or very small (not easy to accomplish). • Can use buffers to reduce the output loading. But additional offset and drift are introduced. • One possible scheme is using separate generators for different parts of system so as to isolate more sensitive circuits from other ones. However, mismatch among generators, area, power, and trimming cost must be considered. Voltage and Current References 9-29 Analog ICs; Jieh-Tsorng Wu Output Stages Jieh-Tsorng Wu ES A December 5, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Output Stage Requirements Io Vi Io Vo Vi Output Vo Output Stage Stage RL CL RL CL • Deliver large output current to low-impedance loads (resistive and/or capacitive). • Usually is a voltage buffer, i.e., low voltage gain, high Zi n, and low Zo. • High Zi n is to maintain voltage gain and bandwidth of previous stage. • Wide bandwidth if in the feedback loop, • May need protection against load shorts. Output Stages 10-2 Analog ICs; Jieh-Tsorng Wu Output Stage Design Issues • Frequency response. • Output impedance. • Output current. • Output voltage range. • Power efficiency. • Distortion. Output Stages 10-3 Analog ICs; Jieh-Tsorng Wu Nonlinearity and Harmonic Distortion For a nonlinear system with input x , the output y can be expressed as: y = a0 + a1 x + a2 x 2 + a3 x 3 + · · · ˆ With a pure sinusoidal input x = v cos ωt , ˆ ˆ ˆ y = a0 + a1v cos ωt + a2v 2 cos2 ωt + a3v 3 sin3 ωt + · · · ˆ3 ˆ2 a3 v a2 v ˆ (1 + cos 2ωt ) + (3 cos ωt + cos 3ωt ) + · · · = a0 + a1v cos ωt + 2 4 = b0 + b1 cos ωt + b2 cos 2ωt + b3 cos 3ωt + · · · where 1 ˆ b0 = a0 + a2v 2 + · · · 2 1 ˆ b2 = a2v 2 + · · · 2 Output Stages 3 ˆ ˆ b1 = a1v + a3v 3 + · · · 4 1 ˆ b3 = a3v 3 + · · · 4 10-4 Analog ICs; Jieh-Tsorng Wu Nonlinearity and Harmonic Distortion The harmonic distortion factors are HD2 HD3 ≡ ≡ b2 1 a2 ˆ ≈ ·v a1 2 b1 b3 b1 1 a3 2 ˆ ≈ ·v 4 a1 The total harmonic distortion (THD) is THD = b2 + b2 + · · · 2 3 b1 The SINAD is the ratio of signal plus noise plus distortion powers to noise and distortion powers, i.e, S +N +D SINAD = N +D Output Stages 10-5 Analog ICs; Jieh-Tsorng Wu Class-A BJT Emitter Follower VCC Vi Q1 Io Vo IQ R3 RL Q2 R1 R2 VCC Vbe1 Ic1 = UT ln IS 1 Output Stages Ic1 Vo = IQ + RL ⇒ Vi = Vo + Vbe1 = Vo + UT ln 10-6 IQ + Vo/RL IS 1 Analog ICs; Jieh-Tsorng Wu Class-A BJT Emitter Follower Output Power Vce1 = VCC − (Ic1 − IQ )RL ˆ For a sinusoidal Vo with amplitudes Vo and Iˆo, 1ˆ ˆ Average Output Power = PL = VoIo 2 Average Supply Power = Psupply = 2VCC IQ Maximum output swing and output power are ˆ Vom = VCC − VCE (sat) = IQ · RL Iˆom = IQ 1ˆ 1 VCC − VCE (sat) IQ PL(max) = Vom Iˆom = 2 2 Power Conversion Efficiency = ηC = Output Stages PL Psupply 10-7 ηC(max) 1 = 4 1− VCE (sat) VCC ≤ 1 4 Analog ICs; Jieh-Tsorng Wu Instantaneous Power Dissipation Q1 Instantaneous Power Dissipation is Pc1 = Vce1 Ic1 At maximum ηC , Pc1 = VCC (1 + sin ωt ) × IQ (1 − sin ωt ) = VCC IQ 2 (1 + cos 2ωt ) • The maximum Pc1 occurs at the midpoint of any load line. Output Stages 10-8 Analog ICs; Jieh-Tsorng Wu Class-A MOST Source Follower VDD Vi M1 I o Vo IQ RL M2 VDD Id 1 = IQ + ⇒ Output Stages Vi = Vo + Vt0 + γ Vo RL Vi = Vo + Vgs1 = Vo + Vt1 + Vov 1 2φf + Vo + VDD − 10-9 2φf + 2 IQ + Vo/RL k (W/L)1 Analog ICs; Jieh-Tsorng Wu Distortion in the MOST Source Follower Since Vi = f (Vo), we have ∞ Vi = VI + vi = bn(vo)n vo = Vo − VO n=0 1 bn = f (n)(VO ) n! ∞ ⇒ vi = bn(vo)n n=1 To find ∞ vo = an(vi )n n=1 use ∞ vi = ∞ bn(vo)n = n=1 am(vi )m bn n=1 n ∞ m=1 = b1a1vi + (b1a2 + b2a2)vi2 + (b1a3 + 2b2a1a2 + b3a3)vi3 + · · · 1 1 Output Stages 10-10 Analog ICs; Jieh-Tsorng Wu Distortion in the MOST Source Follower Matching coefficients, we obtain 1 a1 = b1 a2 = − b2 a3 = b3 1 2b2 2 b5 1 − b3 b4 1 ˆ • Assume RL → ∞, and let VM = VO + VDD + 2φf , vi = vi sin ωt , then a1 = 1 1+ γ −1/2 V 2M a2 = γ −3/2 V 8M 1+ γ 1 a2 ˆ HD2 = ·v = 2 a1 i 16 1+ 5 γ −1/2 V 2M −3/2 VM 1+ γ 1 a3 2 ˆ HD3 = · vi = − 4 a1 64 Output Stages a3 = − 3 γ −1/2 V 2M γ −5/2 V 16 M 10-11 2 γ −1/2 V 2M ˆ · vi −5/2 VM 1+ 4 γ −1/2 V 2M ˆ · vi2 Analog ICs; Jieh-Tsorng Wu Class-A BJT Common-Emitter Stage VCC R1 R2 Q2 R3 IQ Io Vo Vi Q1 VCC RL Io = IQ − Ic1 ⇒ Vo = IoRL = IQ − IS eVi /UT RL Same output power, ηC , and Pc1 as the class-A emitter followers, since Vce1 = VCC − (Ic1 − IQ )RL Output Stages 10-12 Analog ICs; Jieh-Tsorng Wu Distortion in Class-A BJT Common-Emitter Stage Assume the input is Vi = VBE 1 + vi IQ = IS eVBE 1/UT Then, the output voltage is Vo = −RL IS e(VBE 1+vi )/UT − IQ = −RLIQ evi /UT − 1 = −RLIQ vi 1 vi + UT 2 UT 2 1 vi...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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