Analog Integrated Circuits (Jieh Tsorng Wu)

Analog Integrated Circuits(Jieh Tsorng Wu)

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Unformatted text preview: oximation, let |p1| D (s) = |p2| 1 + b1s + b2s2 = s 1− p1 s 1− p2 2 2 s 1 s s 1 =1−s + + ≈1− + p1 p2 p1p2 p1 p1p2 1 1 1 = ≈− b1 R1[C1 + Cf (1 + gmR2)] + R2(C2 + Cf ) R1[C1 + Cf (1 + gmR2)] b1 R1(C1 + Cf ) + R2(C2 + Cf ) + gmR1R2Cf gmCf ≈− p2 ≈ − = b2 C1 C2 + C1Cf + C2Cf R1R2(C1 C2 + C1Cf + C2Cf ) p1 ≈ − • The Miller approximation is a simplified dominant pole approximation. • The Miller approximation results in incorrect estimation for the second pole. Single-T Gain Stages 5-17 Analog ICs; Jieh-Tsorng Wu Common-Emitter Amplifier with Emitter Degeneration Cµ ii io vo vi v1 vo vi rπ Cπ g m v1 ve ro Q1 RE RE ii Cµ RE io vo vi v1 Single-T Gain Stages rπeq 5-18 Cπeq gmeq v1 roeq Analog ICs; Jieh-Tsorng Wu Common-Emitter Amplifier with Emitter Degeneration To find rπeq , Cπeq , and gmeq , let vo = 0, then (gm + gπ + sCπ )(vi − ve) = (GE + go)ve At frequencies where ω ωT = gm/(Cπ + Cµ), gm + gπ + sCπ gm + gπ ve = ≈ vi gm + gπ + GE + go + sCπ gm + gπ + GE + go R gmeq 1− β E r ve −io ve g m GE − g o g π oo − go · = = = gm 1 − = gm · vi vi vi g m + g π + GE + g o 1 1 + gmRE 1 + β + g 1r o ve ii = (gπ + sCπ ) 1 − vi vi = (gπ + sCπ ) 1+ RE ro 1 1 + gmRE 1 + β + g 1r o Single-T Gain Stages 5-19 mo mo Analog ICs; Jieh-Tsorng Wu Common-Emitter Amplifier with Emitter Degeneration • If β0 1, ro RE , and gmro gmeq gm ≈ 1 + gmRE 1 rπeq ≈ rπ (1 + gmRE ) Cπeq Cπ ≈ 1 + gmRE To find roeq , let vi = 0, then (gm + gπ + sCπ + GE )ve = go(vo − ve) go go ve = ≈ vo gm + gπ + GE + go + sCπ gm + gπ + GE + go goeq 1+ gm R E βo ve io g π + GE ve − gm = go · = = go 1 − = go · vo vo vo g m + g π + GE + g o 1 1 + gmRE 1 + β + g 1r o roeq ≈ ro(1 + gmRE ) Single-T Gain Stages if gmRE β0 5-20 roeq ≈ ro(1 + β0) if gmRE mo β0 Analog ICs; Jieh-Tsorng Wu Common-Source Amplifier with Source Degeneration i C i i gd o v i v o v o v i v gs C gs r o v s M1 R R gv gv gs mb s m S S i v i i R C S v gs i gd o v o C r oeq gseq g v meq gs Single-T Gain Stages 5-21 Analog ICs; Jieh-Tsorng Wu Common-Source Amplifier with Source Degeneration To find Cgseq and gmeq , let vo = 0, then (gm + sCgs )(vi − vs ) = (GS + gmb + go)vs At frequencies where ω ωT = gm/Cgs , gm + sCgs vs gm = ≈ vi gm + gmb + GS + go + sCgs gm + gmb + GS + go gmeq vs −io vs g m GS gm −(gmb+go) = = = gm 1 − = vi vi vi gm + gmb + GS + go 1 + (g + g )R + RS m mb S r o vs ii = sCgs 1 − vi vi Single-T Gain Stages = sCgs · 5-22 1 + gmbRS + RS ro 1 + (gm + gmb)RS + RS ro Analog ICs; Jieh-Tsorng Wu Common-Source Amplifier with Source Degeneration • If ro RS , gmeq ≈ Cgseq gm 1 + (gm + gmb)RS 1 + gmbRS = gm 1 + (1 + χ )gmRS 1 + χ gmRS = Cgs · = Cgs · 1 + (gm + gmb)RS 1 + (1 + χ )gmRS To find roeq , let vi = 0, then (gm + gmb + sCgs + GS )vs = go(vo − vs ) go go vs = ≈ vo gm + gmb + GS + go + sCgs gm + gmb + GS + go ve io ve g o GS − (gm + gmb) = goeq = = go 1 − vo vo vo gm + gmb + GS + go roeq = RS + ro[1 + (gm + gmb)RS ] • roeq can be made arbitrarily large by increasing RS . Single-T Gain Stages 5-23 Analog ICs; Jieh-Tsorng Wu Common-Base Configuration VCC vo v1 RL rπ Cπ g m vi VO + vo Q1 vi ro RL CL ii II − ii • It is a current buffer, i.e., current gain 1, low Ri n, and high Rout . • Typically neglect rb, rc, and re, so that v1 = −vi . • Combine Cµ, Ccs , and load capacitance into CL. Single-T Gain Stages 5-24 Analog ICs; Jieh-Tsorng Wu Common-Base Configuration AC Analysis To further simplify the analysis, neglect ro; i.e., assume go(vo − vi ) (gπ + sCπ )vi + gmvi = ii (GL + sCL)vo = gmvi Zt (0) gm 1 × = gm + gπ + sCπ GL + sCL ii (s) 1 − s/p1 1 − s/p2 βo gm + gπ gm 1 gm 1 RL = αoRL p1 = − RL = =− p2 = − Zt (0) = gm + gπ αo Cπ βo + 1 Cπ RLCL αo vi (s) Ri n 1 Input Impedance = Zi n(s) = Ri n = Zi n(0) = rπ = = gm gm ii (s) 1 − s/p1 ⇒ Zt (s) = vo(s) gmvi , then = io(s) αo g m vi Current Gain = = gmZi n(s) = = ii ii (s) 1 − s/p1 • Note that |p1| = (1/αo)(gm/Cπ ) > ωT = gm/(Cπ + Cµ). • Expect |p2 | < |p1| in typical cases. Single-T Gain Stages 5-25 Analog ICs; Jieh-Tsorng Wu Common-Gate Configuration VDD C Vo C gd -g gs v o v m in g o Bias v in I -i IN in g v in R L C L gm = gm + gmb i in C’ CL = Ct + Cgd = CL + Cd b + Cgd v mb in R L C t sb Ci n = Cgs + Csb The nodal equations are ii n = (gm + sCi n )vi n − go(vo − vi n) Single-T Gain Stages gmvi n = (GL + sCL )vo + go(vo − vi n) 5-26 Analog ICs; Jieh-Tsorng Wu Common-Gate Configuration AC Analysis If the go(vo − vi n) terms are neglected, then Transimpedance = Zt (s) = vo ii n = gm gm =− p1 = − Ci n Cgs + Csb Input Impedance = Zi n(s) = RL 1 − s/p1 p2 = − vi n(s) ii n(s) = 1 − s/p2 1 RLCL 1/gm 1 − s/p1 io(s) g m vi n 1 Current Gain = = gmZi n(s) = = ii n ii n(s) 1 − s/p1 • Note that p1 ωT = gm/(Cgs + Cgd ). Single-T Gain Stages 5-27 Analog ICs; Jieh-Tsorng Wu Common-Gate Configuration AC Analysis If go is considered, Voltage Gain = Av (s) = vo gm + go = vi n go + GL + sCL ii n = gm + sCi n − go(Av − 1) vi n vo Av (s) Zt (s) = = ii n Yi n(s) Input Impedance = Yi n(s) = • At low frequencies where ω → 0, assuming gm gm + go Av = ⇒ Single-T Gain Stages Y i n = gm − g o + GL gm 1+ GL go ≈ + go ≈ 5-28 go , gm g o + GL gm 1+ RL ro Av Zt = ≈ RL Yi n Analog ICs; Jieh-Tsorng Wu Common-Collector Configuration (Emitter Follower) Cµ RS ii VCC RS vi Q1 rπ Cπ g...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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