Analog Integrated Circuits (Jieh Tsorng Wu)

10 gain accuracy of g is tolerable oversampling 26 8

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Unformatted text preview: g., Ai = 0 and Ai = Aref . • The effects of noise can be suppressed by averaging a number of successive measurements during calibration. ˆda • During j stage calibration, to avoid overloading the Aj +1 port, different Aj (Dc) measurement may need different Ac value. • On the circuit level, the effectiveness of calibration is limited by noises, interferences, nonlinear Gj , and amplifier transient behavior. ADCs 25-50 Analog ICs; Jieh-Tsorng Wu Calibration of A Radix-2 1.5 Bit SC Pipeline Stage 2 Cf Cf 1 Vj 0.25 Vr Vj+1 0.25 Vr 1 Vr x D j Calibration Phase 1 1 Vc Vj+1 g C g C 2 Calibration Phase 2 Cf Encoder Vj+1 D j = −1, 0, +1 Vr x Dc g C C L ˆda • To calibrate Aj (Dj = 1). Obtain Dz1 by letting Vc = 0.25Vr and Dc = 0, and obtain Dz2 by letting Vc = 0.25Vr and Dc = 1. Then Tj (Dj = 1) = (Dz1 − Dz2)/Gj . ˆda • To calibrate Aj (Dj = −1). Obtain Dz1 by letting Vf = −0.25Vr and Dc = 0, and obtain Dz2 by letting Vc = −0.25Vr and Dc = −1. Then Tj (Dj = −1) = (Dz1 − Dz2)/Gj . ADCs 25-51 Analog ICs; Jieh-Tsorng Wu A Radix-2 Cyclic ADCs Vj+1 Vi Vj S/H x2 VR VR Dj Vj +1 = 2 × Vj − Dj × VR = 2 × Vj + Dj · VR 2 Dj ∈ {+1, −1} • Start with j = 1 and V1 = Vi . • For each cycle, j is increased by 1. ADCs 25-52 Analog ICs; Jieh-Tsorng Wu A Radix-2 Switched-Capacitor Cyclic ADC S4 C2 Vi S1 S6 C1 C6 Dj A1 VR S2 S3 C5 S5 A3 C1 = C2 = C3 = C4 = C C3 C5 = 2C Dj ∈ {1, 0} C4 A2 Vi = VR × N Dj · 2 j =1 ADCs 25-53 −j 1 − 2 Analog ICs; Jieh-Tsorng Wu A Radix-2 Switched-Capacitor Cyclic ADC Input Sampling (1) Input Sampling (2) C1 C2 C1 C6 C6 Vi D1 A1 C5 A1 A3 C5 C3 C3 A2 A2 j-Cycle (2) j-Cycle (1) C6 C1 A3 C2 C1 Vj+1 C6 Dj+1 A1 Dj x VR C5 C4 A3 Dj x VR C3 A3 A1 C3 C5 Vj A2 ADCs A2 25-54 Analog ICs; Jieh-Tsorng Wu A CMOS Subranging Flash ADC — Dingwall Vi VR 1 1 2 1 1 VK 2 VK 1 1 2 M-ADC Comparator Bank 3 1 3 1 ADCs 1 3 1 1 3 1 1 25-55 1 L-ADC Comparator Bank Analog ICs; Jieh-Tsorng Wu A CMOS Subranging Flash ADC — Dingwall • Two-Stage quantized-feedforward architecture. M – The first-stage M-ADC has 2 − 1 comparators, and G1 = 1. L – The second-stage L-ADC has 2 − 1 comparators. – For minimal design, Do has N = M + L bits. • The S/H and the subtractor function is embedded in every comparator. Require no additional subtractor or DAC. • Comparators in both M-ADC and L-ADC need to have N-bit accuracy. • The input range of the L-ADC can be extended to prevent over-loading. The accuracy requirement for the M-ADC can then be relaxed. • Reference: A. Dingwall, et. al., “An 8-MHz CMOS Subranging 8-Bit A/D Converter,” JSSC 12/1985, pp. 1138–1143. ADCs 25-56 Analog ICs; Jieh-Tsorng Wu A CMOS Subranging Flash ADC — Brandt ADCs 25-57 Analog ICs; Jieh-Tsorng Wu Interpolated Differential Comparator Bank ADCs 25-58 Analog ICs; Jieh-Tsorng Wu A CMOS Subranging Flash ADC — Brandt • Two-stage quantized-feedforward differential architecture. • The voltage ranges are Ci n+ − Ci n− = [−2 ↔ +2] and Fi n+ − Fi n− = [0 ↔ +2]. • The absolute-value processing reduces the number of switches in the AMUXs by half. In addition, the settling time of the AMUX outputs is also reduced due to the reduction in output voltage swing and output capacitive loading. • The interpolation scheme can reduce the number of “taps” from the reference ladder and reduce the number of preamplifiers. It also attenuates front-end sources of DNL, such as mismatches in the input sampling switches and resistor mismatch in the reference ladder. • Reference: B. Brandt, et. al., “A 75-mW, 10-b 20-MSPS CMOS Subranging ADC,” JSSC 12/1999, pp. 1788–1795. ADCs 25-59 Analog ICs; Jieh-Tsorng Wu Flash Quantization Architecture 0 VRB 1 2 3 4 5 6 7 VRT Vi 0 1 V0 2 3 V2 4 5 V4 6 7 V6 Thermometer-to-Binary Encoder V0 V2 V4 0 Do Thermometer Code 00000000 10000000 1 11000000 2 11100000 3 11110000 4 11111000 5 11111100 6 11111110 7 11111111 Vi ADCs V6 N 25-60 Analog ICs; Jieh-Tsorng Wu Resistor-String Interpolation 0 VRB 1 2 3 4 5 7 6 VRT Vi 0 2 V0 4 V2 6 V4 V6 Thermometer-to-Binary Encoder V0 V2 V4 0 Do Thermometer Code 00000000 10000000 1 11000000 2 11100000 3 11110000 4 11111000 5 11111100 6 11111110 7 11111111 Vi ADCs V6 N 25-61 Analog ICs; Jieh-Tsorng Wu Folding 0 VRB 1 2 3 4 5 6 7 8 VRT Vi 0 4 1 V0 5 V1 2 6 V2 V1 V2 N V3 Do Circular Code 0000 0 1000 1 1100 2 1110 3 1111 4 0111 5 0011 6 0001 7 0000 Vi ADCs 7 V3 Circular-to-Binary Encoder V0 3 25-62 Analog ICs; Jieh-Tsorng Wu Interpolation and Folding • The number of latch comparators is reduced by folding, while the number of folding blocks is reduced by interpolation. • The interpolation can reduce the input capacitances for Vi , VRT , and VRB , since the number of the preamplifers is reduced. The interpolation can improve the DNL, due to the redistribution of mismatch errors. • The interpolation technique can also be used with other types of signals, such as currents and charges. • The folding circuit need only to be accurate near the zero-crossing points. ADCs 25-63 Analog ICs; Jieh-Tsorng Wu Averaging Preamplifiers VDD VDD VDD R R R R R R R R I VSS I VSS I VSS • The outputs are connected by interpolating resistor string. • Gain is determined by R × I . • Speed is determined by R × C. ADCs 25-64 Analog ICs; Jieh-Tsorng Wu Effects of Averaging Input and Reference R-String Averaging R-String Io m=5 Vi Input Range • Differential nonlinearity (DNL) improves with m. • Integral nonlinearity...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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