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Unformatted text preview: g., Ai = 0 and Ai = Aref . • The eﬀects of noise can be suppressed by averaging a number of successive
measurements during calibration.
ˆda
• During j stage calibration, to avoid overloading the Aj +1 port, diﬀerent Aj (Dc)
measurement may need diﬀerent Ac value.
• On the circuit level, the eﬀectiveness of calibration is limited by noises, interferences,
nonlinear Gj , and ampliﬁer transient behavior. ADCs 2550 Analog ICs; JiehTsorng Wu Calibration of A Radix2 1.5 Bit SC Pipeline Stage
2 Cf Cf 1 Vj
0.25 Vr Vj+1 0.25 Vr
1
Vr x D j Calibration Phase 1 1 Vc Vj+1
g C
g C 2 Calibration Phase 2
Cf Encoder Vj+1 D j = −1, 0, +1
Vr x Dc g C C L ˆda
• To calibrate Aj (Dj = 1). Obtain Dz1 by letting Vc = 0.25Vr and Dc = 0, and obtain Dz2
by letting Vc = 0.25Vr and Dc = 1. Then Tj (Dj = 1) = (Dz1 − Dz2)/Gj .
ˆda
• To calibrate Aj (Dj = −1). Obtain Dz1 by letting Vf = −0.25Vr and Dc = 0, and obtain
Dz2 by letting Vc = −0.25Vr and Dc = −1. Then Tj (Dj = −1) = (Dz1 − Dz2)/Gj .
ADCs 2551 Analog ICs; JiehTsorng Wu A Radix2 Cyclic ADCs Vj+1
Vi Vj
S/H x2 VR VR Dj Vj +1 = 2 × Vj − Dj × VR = 2 × Vj + Dj · VR
2 Dj ∈ {+1, −1} • Start with j = 1 and V1 = Vi .
• For each cycle, j is increased by 1.
ADCs 2552 Analog ICs; JiehTsorng Wu A Radix2 SwitchedCapacitor Cyclic ADC
S4
C2
Vi S1 S6 C1 C6
Dj
A1 VR S2 S3 C5 S5 A3 C1 = C2 = C3 = C4 = C C3 C5 = 2C
Dj ∈ {1, 0} C4 A2 Vi = VR × N Dj · 2
j =1 ADCs 2553 −j 1
−
2
Analog ICs; JiehTsorng Wu A Radix2 SwitchedCapacitor Cyclic ADC
Input Sampling (1) Input Sampling (2) C1 C2 C1 C6 C6 Vi D1
A1
C5 A1 A3
C5 C3 C3 A2 A2
jCycle (2) jCycle (1)
C6 C1 A3 C2 C1 Vj+1 C6
Dj+1 A1 Dj x VR
C5 C4 A3 Dj x VR C3 A3 A1
C3 C5 Vj
A2 ADCs A2 2554 Analog ICs; JiehTsorng Wu A CMOS Subranging Flash ADC — Dingwall
Vi
VR 1
1
2
1
1 VK 2 VK 1
1
2 MADC
Comparator Bank
3 1 3 1 ADCs 1 3 1 1 3 1 1 2555 1 LADC
Comparator Bank Analog ICs; JiehTsorng Wu A CMOS Subranging Flash ADC — Dingwall
• TwoStage quantizedfeedforward architecture.
M – The ﬁrststage MADC has 2 − 1 comparators, and G1 = 1.
L
– The secondstage LADC has 2 − 1 comparators.
– For minimal design, Do has N = M + L bits.
• The S/H and the subtractor function is embedded in every comparator. Require no
additional subtractor or DAC.
• Comparators in both MADC and LADC need to have Nbit accuracy.
• The input range of the LADC can be extended to prevent overloading. The accuracy
requirement for the MADC can then be relaxed.
• Reference: A. Dingwall, et. al., “An 8MHz CMOS Subranging 8Bit A/D Converter,”
JSSC 12/1985, pp. 1138–1143. ADCs 2556 Analog ICs; JiehTsorng Wu A CMOS Subranging Flash ADC — Brandt ADCs 2557 Analog ICs; JiehTsorng Wu Interpolated Diﬀerential Comparator Bank ADCs 2558 Analog ICs; JiehTsorng Wu A CMOS Subranging Flash ADC — Brandt
• Twostage quantizedfeedforward diﬀerential architecture.
• The voltage ranges are Ci n+ − Ci n− = [−2 ↔ +2] and Fi n+ − Fi n− = [0 ↔ +2].
• The absolutevalue processing reduces the number of switches in the AMUXs by half.
In addition, the settling time of the AMUX outputs is also reduced due to the reduction
in output voltage swing and output capacitive loading.
• The interpolation scheme can reduce the number of “taps” from the reference ladder
and reduce the number of preampliﬁers. It also attenuates frontend sources of DNL,
such as mismatches in the input sampling switches and resistor mismatch in the
reference ladder.
• Reference: B. Brandt, et. al., “A 75mW, 10b 20MSPS CMOS Subranging ADC,”
JSSC 12/1999, pp. 1788–1795. ADCs 2559 Analog ICs; JiehTsorng Wu Flash Quantization Architecture
0 VRB 1 2 3 4 5 6 7 VRT Vi
0 1 V0 2 3 V2 4 5 V4 6 7 V6 ThermometertoBinary Encoder
V0 V2 V4 0 Do Thermometer Code
00000000
10000000 1 11000000 2 11100000 3 11110000 4 11111000 5 11111100 6 11111110 7 11111111 Vi ADCs V6 N 2560 Analog ICs; JiehTsorng Wu ResistorString Interpolation
0 VRB 1 2 3 4 5 7 6 VRT Vi
0 2 V0 4 V2 6 V4 V6 ThermometertoBinary Encoder
V0 V2 V4 0 Do Thermometer Code
00000000
10000000 1 11000000 2 11100000 3 11110000 4 11111000 5 11111100 6 11111110 7 11111111 Vi ADCs V6 N 2561 Analog ICs; JiehTsorng Wu Folding
0 VRB 1 2 3 4 5 6 7 8 VRT Vi
0 4 1 V0 5 V1 2 6 V2 V1 V2 N V3 Do
Circular Code
0000 0 1000 1 1100 2 1110 3 1111 4 0111 5 0011 6 0001 7 0000 Vi ADCs 7 V3 CirculartoBinary Encoder
V0 3 2562 Analog ICs; JiehTsorng Wu Interpolation and Folding
• The number of latch comparators is reduced by folding, while the number of folding
blocks is reduced by interpolation.
• The interpolation can reduce the input capacitances for Vi , VRT , and VRB , since the
number of the preamplifers is reduced.
The interpolation can improve the DNL, due to the redistribution of mismatch errors.
• The interpolation technique can also be used with other types of signals, such as
currents and charges.
• The folding circuit need only to be accurate near the zerocrossing points. ADCs 2563 Analog ICs; JiehTsorng Wu Averaging Preampliﬁers
VDD VDD VDD R R R R R R R R I
VSS I
VSS I
VSS • The outputs are connected by interpolating resistor string.
• Gain is determined by R × I .
• Speed is determined by R × C.
ADCs 2564 Analog ICs; JiehTsorng Wu Eﬀects of Averaging
Input and Reference RString Averaging RString
Io
m=5
Vi Input Range • Diﬀerential nonlinearity (DNL) improves with m.
• Integral nonlinearity...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.
 Winter '09
 Choma
 Integrated Circuit, Transistor, The Land

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