Analog Integrated Circuits (Jieh Tsorng Wu)

1npn 1pnp r r 01 2 if gmr 1 the ic mismatch

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Unformatted text preview: erential Gain Stages 7-28 vi d =0 iˆc = iˆd = gmvi d g m vi c 1 + 2gmRSS gm∆R + ∆gmR =− 1 + 2gmRSS ∆gmR 1 gm∆R + =− 4 1 + 2gmRSS vi c =0 Analog ICs; Jieh-Tsorng Wu Current Mirrors and Active Loads Jieh-Tsorng Wu ES A November 7, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Simple BJT Current Mirror VCC βF 1 = βF 2 = βF IC2 IIN VA1 = VA2 = VA Vo IC1 = IS 1 e IC2 = IS 2 e IC2 IC1 Q1 Q2 IB1 Vo IB2 VCE (sat) IC2 = IC1 IS 2 IS 1 1+ VCE 2 − VCE 1 VA + VCE 1 VBE /UT VBE /UT IC2 = IIN · IS 1 · (1 + ) Ro2 = ro2 Current Mirrors 1+ VA VCE 2 IIN = IC1 + IB1 + IB2 = IC1 + = IIN · IS 2 1+ · IS 1 1 + 1 + 1 β β = Systematic Gain Error ≈ Vo(mi n) = VCE 2(sat) 8-2 1+ VCE 2 − VCE 1 VCC(mi n) VA IC1 βF + IC2 βF VCE 2 −VCE 1 VA+VCE 1 IS 2 F IS 1 F IS 2 1+ VCE 1 VCE 2 −VCE 1 VA +VCE 1 1 − βF VA = VBE 1(on) 1+ IS 2 IS 1 Analog ICs; Jieh-Tsorng Wu Simple BJT Current Mirror with Beta Helper • Ignore Early effect. For Q1 and Q2, let VCC βF 1 = βF 3 = βF Vo IIN IC3 IC1 = IS 3 IS 1 Q2 IC1 IC3 Q1 • From KCL, Q3 IB1 IB3 IC3 = IC1 IS 3 IS 1 IIN = IC1 + = IIN · IS 3 · IS 1 1 + β ≈− Ro3 = ro3 Current Mirrors Vo(mi n) IB1 + IB3 βF 2 + 1 1 1 F (βF 2 +1) 1 1+ 1+ IS 3 IS 1 = IC1 + 1 βF (βF 2 + 1) = IIN · IS 3 IS 1 (IC1 + IC3 ) · (1 + ) IS 3 IS 1 βF (βF 2 + 1) = VCE 3(sat) VCC(mi n) = VBE 1(on) + VBE 2(on) 8-3 Analog ICs; Jieh-Tsorng Wu Simple BJT Current Mirror with Emitter Degeneration VCC VB = IC1R1 + UT ln IIN IC3 IC4 IC1R1 Q2 Q3 If Q1 Q4 R1 VB R3 R4 Ro3 ≈ ro3(1 + gm3R3) = ro3 1 + IS 1 = IC3R3 + UT ln − 1 = UT ln IC1 IS 3 IS 3 R1 = IS 1 R3 then IC3 IC1 IC3 IS 3 IC1 IS 3 IC3 IS 1 IS 3 = IS 1 • The BJT should be scaled with corresponding emitter resistor. IC3R3 Vo(mi n) = VCE 3(sat) + IC3R3 Current Mirrors IC3 IS 1 IC1 |βF =∞ = UT VCE 3 − VCE 1 VA(1 + gm3RE ) = VCE 3 − VCE 1 VA 1 + IC 3 R 3 UT VCC(mi n) = VBE 1(on) + VBE 2(on) + IC1R1 8-4 Analog ICs; Jieh-Tsorng Wu Matching Consideration in BJT Current Mirrors Assume Q3 Q4, and let ∆IC ≡ IC3 − IC4 ∆IS ≡ IS 3 − IS 4 ∆αF ≡ αF 3 − αF 4 IC3 + IC4 IS 3 + IS 4 αF 3 + αF 4 IS ≡ αF ≡ IC ≡ 2 2 2 To calculate mismatch between IC3 and IC4, VB = VBE 3 + IE 3 R3 = VBE 4 + IE 4R4 = UT ln UT ln UT ln IC + ∆IC 2 ∆IC 2 − UT ln IC3 IC4 − UT ln IS + ∆IS 2 ∆IS 2 IS 3 IS 4 + IC3 IS 3 ∆R ≡ R3 − R4 R3 + R4 R≡ 2 IC3 IC4 IC4 + R = UT ln + R αF 3 3 IS 4 αF 4 4 IC3 IC4 + R− R =0 αF 3 3 αF 4 4 IC + ∆IC 2 R + ∆R 2 ∆αF 2 − IC − ∆IC 2 R − ∆R 2 ∆αF 2 αF + αF − IS − ∆IC ∆R ∆αF IC R ∆IC ∆R ∆αF ∆IC ∆IS IC R 1+ − 1− UT − + − UT + + − αF αF IC IS 2IC 2R 2αF 2IC 2R 2αF IC − Current Mirrors 8-5 =0 =0 Analog ICs; Jieh-Tsorng Wu Matching Consideration in BJT Current Mirrors With above approximations, we obtain ∆IC IC ≈ 1 1+ gm R αF gm R αF ∆IS ∆R ∆αF − + + gm R αF IS R 1+ α F For a typical bipolar process ∆IS IS ±1% − ±10% ∆αF αF ±0.1%(npn) ± 1%(pnp) ∆R R ±0.1% − ±2% • If gmR 1, the IC mismatch is determined by IS mismatch. • If gmR 1, the IC mismatch is determined by R and αF mismatches. Current Mirrors 8-6 Analog ICs; Jieh-Tsorng Wu Simple MOST Current Mirror IIN ID2 VD1 M1 VD3 VD2 VR M2 ID3 M3 k = µnCox 1 IIN = k 2 1 ID2 = k 2 1 ID3 = k 2 W L W L W L (VR − Vt1 )2(1 + λ1VD1) 1 (VR − Vt2 )2(1 + λ2VD2) 2 (VR − Vt3 )2(1 + λ3VD3) 3 Let Vt1 = Vt2 = Vt and λ1 = λ2 = λ, then ID2 (W/L)2 1 + λVD2 (W/L)2 = IIN · · = IIN · · (1 + ) 1 + λVD1 (W/L)1 (W/L)1 Ro2 = ro2 1 = λ2ID2 Current Mirrors Vo2(mi n) = Vov 2 ≈ Vov 1 ≈ 8-7 2IIN k (W/L)1 VD2 − VD1 ≈ λ(VD2 − VD1) = VA VDD(mi n) = VGS 1 = Vt + Vov 1 Analog ICs; Jieh-Tsorng Wu Matching Consideration in Simple MOST Current Mirror Ignore λ effects. Assume M2 M3, and let ∆ID ≡ ID2 − ID3 ID2 + ID3 ID ≡ 2 ∆(W/L) ≡ (W/L)2 − (W/L)3 ∆Vt ≡ Vt2 − Vt3 (W/L)2 + (W/L)3 (W/L) ≡ 2 Vt2 + Vt3 Vt ≡ 2 VR = Vt2 + Vov 2 = Vt3 + Vov 3 = Vt2 + 2ID2 k (W/L)2 = Vt3 + 2ID3 k (W/L)3 Neglecting all second order terms, we obtain ∆Vt ∆ID ∆(W/L) = − ID (W/L) Vov /2 Vov = 2ID k (W/L) • To maximize output swing, want a small Vov . But then ∆ID /ID increases as Vov decreases for a given ∆Vt . Current Mirrors 8-8 Analog ICs; Jieh-Tsorng Wu Layout Considerations VDD VDD Vg Vs V’s Voltage Routing Current Mirrors V’’s VSS VSS Current Routing 8-9 Analog ICs; Jieh-Tsorng Wu BJT Cascode Current Mirror IIN Vo vo Io Q4 Q2 Q3 Q1 vo io gm2v2 rπ2 gm2v2 ro2 gm1v1 rπ1 gm1v1 ro1 v2 rπ2 io gm2v2 ro2 rex ro1 1 gm1 gm2 g m1 1 1 ≈ = gm2 ⇒ ≈ gm1 ≈ ⇒ RE = ro1 rex ≈ rπ2 1 1 rex βo2 + 2 rπ2 rπ2 + g + g m2 m 1 βr βr gR 1 + m2 E ≈ ro2 1 + o2 π2 ≈ o2 o2 Ro ≈ ro2 gR rπ2 + rπ2 2 1 + m2 E β o2 Vo(mi n) = VCE 1 + VCE 2(sat) ≈ VBE 3(on) + VCE 2(sat) Current Mirrors 8-10 VCC(mi n) = VBE 3(on) + VBE 4(on) Analog ICs; Jieh-Tsorng Wu BJT Cascode Current Mirror Neglect Early effect. Let Q1=Q3, IC3 = IC1 IC2 = IC1 βF βF = IC3 βF + 1 βF + 1 From KCL, IIN = IC4 + IB4 + IB2 = IC3 + IB3 + IB1 + IB2 = IC3 + IC3 βF + IC3 βF + IC3 βF + 1 Thus IC2 βF βF = IIN · · = IC3 βF + 1 βF + 1 1 + IC2 = IIN (1 + ) Current Mirrors ⇒ 1 2 βF + 1 βF + 1 = IIN · 1− 4βF + 2 2 βF + 4βF + 2 4βF + 2 4 =− ≈− 2 βF + 4 β F + 4β F + 2 8-11 Analog ICs; Jieh-Tsorng Wu MOST Cascode Current Mirror V IIN I V1 M4 -g o v m2 2 g i o v mb2 2 v o g o2 M2 V2 M3 o V v 2 M1 3 g o...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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