Analog Integrated Circuits (Jieh Tsorng Wu)

2 v o g o2 v 2 2 g o3 g v m3 2 g g o1 m1 ro ro2 1

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Unformatted text preview: 1 Ro = ro1ro2 (gm2 + gmb2 + go1 + go2) ≈ ro1ro2gm2(1 + χ2) Vo(mi n) = VDS 1 + VDSAT 2 = Vt3 + Vov 3 + Vov 2 VDD(mi n) = VGS 3 + VGS 4 = Vt3 + Vt4 + Vov 3 + Vov 4 0 Current Mirrors 8-12 Analog ICs; Jieh-Tsorng Wu MOST High-Swing Cascode Current Mirror 1 (W/L)4 = (W/L) 4 ⇒ VGS 4 = Vt + 2Vov VDD VDD I Vo IN I I V V o t M4 M2 Vov M3 Vo IN M1 2 W 4L V I M5 M4 V M2 M6 V1 = Vt + Vov V 3 1 M3 o V2 = 2Vt + 3Vov 4 M1 V3 = Vt + 2Vov V4 = Vov Vo(mi n) = VDS 1 + VDSAT 2 = 2Vov VDD(mi n) = VGS 3 + VGS 4 = 2Vt + 3Vov VDS 1 − VDS 3 Vov − (Vt + Vov ) Vt ≈ ≈ =− VA VA VA • In practice, select (W/L)4 < (1/4)(W/L) due to body effect and design margin. Current Mirrors 8-13 Analog ICs; Jieh-Tsorng Wu MOST Sooch Cascode Current Mirror VDD I VDD I IN IN VB MB 1 IIN = k 2 V 2 =k W L M6 VA W MA 3L M4 V ⇒ Vo W M5 3L V 1 I V o M2 3 5 M3 V 1W 4L 1W 3L (VB − Vt )2 2 (VB − Vt )VA − 2VA VB = Vt + 2Vov VA = Vov V1 = Vt + Vov V2 = 2Vt + 3Vov V3 = Vt + 2Vov 4 M1 V4 = Vov V5 = Vov Vo(mi n) = VDS 1 + VDSAT 2 = 2Vov Current Mirrors VDD(mi n) = V2 = 2Vt + 3Vov 8-14 =0 Analog ICs; Jieh-Tsorng Wu MOST Low-Voltage High-Swing Cascode Current Mirror V1 = Vt + Vov VDD I I IN V2 = Vt + 2Vov Vo IN V3 = Vov I W 4L M5 V 2 M2 M4 V V 4 M3 V4 = Vov o V 3 Vo(mi n) = VDS 1 + VDSAT 2 = 2Vov M1 VDD(mi n) = V2 = Vt + 2Vov 1 =0 • In practice, select (W/L)5 < (1/4)(W/L) due to body effect and design margin. • To bias M2 and M4 in the active region, want V2 − V1 < Vt Current Mirrors 8-15 ⇒ Vov < Vt . Analog ICs; Jieh-Tsorng Wu ¨ Sackinger Current Mirror VDD VDD Vo I in Io VDD I B2 I B1 M2 M1 M6 VSS ⇒ 1 If A = gm5ro5 2 1 Ro ≈ gm1gm5ro1ro3ro5 2 M5 M4 M3 VSS Vo(mi n) = VGS 5 + VDSAT 1 = Vov 1 + Vov 5 + Vt VDD(mi n) = VGS 5 + VV GS 1 = Vov 1 + Vov 5 + 2Vt VSS • It may be necessary to add local compensation capacitors to the enhancement loops to prevent ringing during transients. • The scheme can substantially slow down the settling times for large-signal transients. A typical settling-time might be increased by 50%. Current Mirrors 8-16 Analog ICs; Jieh-Tsorng Wu Gatti Current Mirror VDD Vo VDD I in IB VDD Io 4IB 4IB M2 M8 IB VGS 5 = Vov 3 + Vov 7 + Vt ⇒ VDS 3 = Vov 3 M1 M6 M5 VSS M7 Vo(mi n) = VDS 3 + VDSAT 1 VSS = Vov 1 + Vov 3 M4A M4 M3A M3 VDD(mi n) = VGS 5 = Vov 3 + Vov 7 + Vt VSS • If (W/L)1,2,3,4 = n × (W/L)5,6,7,8,3A,4A, keep Ii n < nIB . • M2 can be a fixed-bias cascode. The resulting circuit is less prone to instability. Current Mirrors 8-17 Analog ICs; Jieh-Tsorng Wu BJT Wilson Current Mirror IIN Vo vo Io v2 Q2 Q3 Q1 io βo2ro2 Ro ≈ 2 Vo(mi n) = VBE 1(on) + VCE 2(sat) gm2v2 ro2 rπ2 Ri n gm3v1 VDD(mi n) = VBE 1(on) + VBE 2(on) v1 gm1 VBE 2 − + 2 VA βF + 2βF + 2 2 ≈− Assume Q1=Q2=Q3, then IC1 = IC3 , and IIN = IC3 + IC2 βF = IC1 + IC2 βF IO = IC2 = IIN Current Mirrors IC2 = −IE 2 1− βF 2 = IC1 1 + βF + 1 βF 2 2 βF + 2βF + 2 8-18 = βF βF + 1 IIN 1+β 2 (βF +2) F Analog ICs; Jieh-Tsorng Wu MOST Wilson Current Mirror IIN V Vo I 1 M4 V o g v mb4 3 in g v 1 M2 g o4 3 M3 R V M1 g m4 v 3 g v v m2 ( 1 - 2 ) v mb2 2 v o g o2 v 2 2 g o3 g v m3 2 g g o1 m1 Ro ≈ ro2 1 + gm3 gm2 gm2 (1 + χ2) + · G i n + g m4 gm1 gm1 G + g · in o3 g (1+χ ) m4 ≈0 Current Mirrors i o Vo(mi n) = VGS 1 + VDSAT 2 8-19 4 VDD(mi n) = VGS 1 + VGS 2 Analog ICs; Jieh-Tsorng Wu Complementary Current Source Load VDD C M2 Vi v i Vo v o C M1 Ro2 gd1 C C’ L gs1 L g GL = go1 + Go2 v m1 i g o1 CL = CL + Co2 • The Vo range in normal operation is between VDSAT 1 and VDD − Vo2(mi n). Current Mirrors 8-20 Analog ICs; Jieh-Tsorng Wu Current Mirror Load VDD Vi M0 R L Vo M2 M1 C L g v m0 i g o0 g v o Neglect Cgd 2 g o1 m1 C t1 g v m2 1 g o2 R L C t2 Ct1 = Cgs1 + Cgs2 + Cd b0 + Cd b1 + · · · = K Cgs1 GL = go2 + GL AI (0) = i o gd2 i i G1 = gm1 + go1 + go0 ⇒ Ct2 = CL + Cd b2 + · · · AI (s) ≡ io ii = vo =0 gm2 gm2 1 = · gm1 1 + go1 + go0 G1 g g m1 Current Mirrors C v 1 m1 8-21 gm2 AI (0) = G1 + sCt1 1 − s/p1 p1 = G1 gm1 ωT 1 ≈ = Ct1 K Cgs1 K Analog ICs; Jieh-Tsorng Wu Diode-Connected Load VDD Vo -g M1 Off VDD Vt2 M2 Vi C M1 Sat’d Vo C M1 Linear L v o C’ L gs1 Vi Vt1 g o2 gd1 v i C M1 vg v m2 o mb2 o g v m1 i g o1 GL = gm2 + gmb2 + go1 + go2 CL = CL + Cd b1 + Cgs2 + Csb2 gm1 gm1 gm1 Av (0) = − =− ≈− gm2 + gmb2 + go1 + go2 gm2 + gmb2 GL gm1 1 Av (0) ≈ − gm2 1 + χ2 Current Mirrors =− 2k1ID1 1 2k2ID2 1 + χ2 8-22 =− (W/L)1 (W/L)2 1 1 + χ2 Analog ICs; Jieh-Tsorng Wu Voltage and Current References Jieh-Tsorng Wu ES A November 13, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Sensitivity and Temperature Coefficient • The sensitivity of a parameter y to a second one x is defined as y Sx ≡ ∆y y ∆x x = x ∂y · y ∂x • The variation of a parameter y that results from changes in temperature is usually characterized by its fractional temperature coefficient, which is defined as the fractional change per degree centigrade change in temperature. TCy ≡ Voltage and Current References ∆y y ∆T 9-2 = 1 ∂y · y ∂T Analog ICs; Jieh-Tsorng Wu Simple Current...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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