Analog Integrated Circuits (Jieh Tsorng Wu)

5 bit sc pipeline stage 2 1 cf conversioin phase 1 1

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Unformatted text preview: πT1f ADCs 25-15 Analog ICs; Jieh-Tsorng Wu Parallel (Flash) Architectures Vref Vi 1 2N -2 2 N ( 2 -1 ) - to - N 2N -1 Encoder N Do ADCs 25-16 Analog ICs; Jieh-Tsorng Wu Parallel (Flash) Architectures • All subregions are examined simultaneously. One comparator per subregion. N N • Using 2 − 1 comparators, the input is simultaneously compared with 2 − 1 reference voltages derived from resistor string. • High speed. Requires only one comparison cycle per conversion. • Large size and power dissipation for large N . • Design issues: input capacitive loading, clock jitter and dispersion, slew-dependent sampling point, nonlinear input capacitance, resistor-string dc and ac bowing, substrate and power-supply noises, kickback noises, sparkles in thermometer code. • Gray encoding is often used as an intermediate step between thermometer and binary codes. ADCs 25-17 Analog ICs; Jieh-Tsorng Wu Successive Approximation Architectures VDA Vi VFS VDA Vref V i 1/2 DAC 3/4 5/8 7/16 t CLK Control Logic b N-1 =1 b N b N-2 =0 N-3 =1 b N-4 =1 Do ADCs 25-18 Analog ICs; Jieh-Tsorng Wu Successive Approximation Architectures • Binary search of possible subregions. • Fraction of VF S corresponding to each bit is successively (starting with MSB) added to fraction corresponding to already determined bits and sum is compared to input. • N comparisons per conversion. • Requires a high-speed DAC with precision on the order of the converter itself. • Excellent trade-off between accuracy and speed. ADCs 25-19 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution ADC Cp Sx Vx 2N-1 C C N-1 SN-1 22C C 2 S2 21C C 1 S1 MSB 20C C 0A S0A S0B LSB Vref 20C C 0B 1 Vref 2 Vi Si N −1 Ctot = 2i Ci + C0A + C0B = 2N C i =1 ADCs 25-20 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution ADCs Sample Mode • Sx → GND. Vx = 0. • S0A, S0B , S1, S2, · · · , SN −1, Si → Vi . Hold Mode • Sx open. • S0A, S1, S2, · · · , SN −1 → GND. • S0B → − 1 Vref , sets transition offset to 1 ∆. 2 2 C0B Vref 1 Vref = −Vi − · · Vx = −Vi − 2 2N Ctot 2 ADCs 25-21 ∆= Vref 2N Analog ICs; Jieh-Tsorng Wu Charge-Redistribution ADCs Redistribution Mode • Si → Vref . • Test bits one at a time in succession, beginning with bN −1. Bit bN −1 Test • SN −1 → Vref 1 Vref CN −1 1 Vref Vref Vx = −Vi − + · Vref = −Vi − · + N N 22 22 2 Ctot • If Vx < 0, bN −1 = 1, SN −1 → Vref . If Vx > 0, bN −1 = 0, SN −1 → GND. ADCs 25-22 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution ADCs Bit bi Test, i = N − 2, N − 3, · · · , 0 • Si → Vref 1 Vref Vref Vx = −Vi − + N 22 2N N −1 Ci 1 Vref Vref bj 2j + · Vref = −Vi − · + bj 2j + 2i 2 2N Ctot 2N j =i +1 j =i +1 N −1 • If Vx < 0, bi = 1, Si → Vref . If Vx > 0, bi = 0, Si → GND. The effect of parasitic capacitance, CP • The voltage on the summing node becomes Vx = Vx · C Ctot . tot +Cp • Cp has no effect on the A/D quantization characteristic, if the comparator is ideal. • CP does attenuate Vx , thus requiring higher comparator gain. ADCs 25-23 Analog ICs; Jieh-Tsorng Wu C-R ADCs Using Input Offset Storage Technique Sx Vx A VOS Capacitor Array • Non-zero comparator offset can be cancelled by referencing Vx to the offset, rather than GND during sampling. ADCs 25-24 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs Sx Vx M-DAC 2M-1 CM-1 21 C1 20 C0C 20 C0 Data Register EN-i Successive Approximation Control Calibration Control L-DAC Do Calibration DAC Calibration Basic Concept Vx Vx C <C A B C =C A B C A V ref (a) Initialize ADCs C B C C A V ref (b) Switch 25-25 t B C >C A B Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs • The error voltage Vx , thus the capacitor mismatch, can be digitized by the Calibration DAC. • During the calibration, the capacitor mismatches in CM −1, CM −2, · · · , C0 are measured sequentially, and stored in the data register. • During the normal operation, the calibration DAC generate a correction voltage that compensates the error voltage caused by the mismatches in the capacitor array • The binary-weighted capacitor array has an accuracy of about 10 bits. With selfcalibration, 16-bit resolution is possible. • Reference: H-S Lee, JSSC 12/84, pp. 813–819. ADCs 25-26 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs Let Ctot = CM −1 + CM −2 + · · · + C1 + C0 + C0C + Cp Capacitor CM −1 calibration CA = CM −1 1 ≡ Ctot + ∆CM −1 2 1 CB = CM −2 + · · · + C1 + C0 + C0C = Ctot − ∆CM −1 2 2∆CM −1 CA − CB Vx = −Vref · = −Vref · Ctot Ctot • Using the C-DAC to digitize Vx , we obtain Dx . • Store EM −1 in the data register as ∆CM −1 1 EM −1 = Dx = −Vref · 2 Ctot ADCs 25-27 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs Capacitor CM −2 calibration 1 CA = CM −2 ≡ Ctot + ∆CM −2 4 1 CB = CM −3 + · · · + C1 + C0 + C0C = Ctot − ∆CM −1 − ∆CM −2 4 ∆CM −1 + 2∆CM −1 CA − CB Vx = −Vref · = −Vref · Ctot Ctot • Using the C-DAC to digitize Vx , we obtain Dx...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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