Analog Integrated Circuits (Jieh Tsorng Wu)

A0 decreases at higher oscillation frequencies oscs

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Unformatted text preview: set Cancellation φ1 = 1 C C V 1 C V 1 1 2 V a2 1 1 V o2 i2 C 2 C C 6 4 V o1 a2 V o2 i2 C 5 a1 5 i1 C 2 C V o1 i1 2 V C 1 C 1 a1 3 1 C 3 6 4 φ2 = 1 C 1 C 3 C 1 5 V o1 2 1 a1 a2 V o2 C Comparators 18-34 2 C C 6 4 Analog ICs; Jieh-Tsorng Wu A Sampled-Data Amplifier with Internal Offset Cancellation • During reset mode, OOS is applied to a1 and IOS is applied to a2. a1 is low gain and a2 is high gain. • The OOS and IOS perform correlated double sampling (CDS) so that the effect of 1/f noise is also reduced. • Additional capacitors in the signal path (i.e., C5 and C6) can degrade the closed-loop settling behavior. • Reference: Yen, JSSC, 12/82, pp. 1008–1013. Comparators 18-35 Analog ICs; Jieh-Tsorng Wu Operational Amplifier with Offset Compensation S1 Vi 1 S3 2 Vo S2 1 S4 G m1 R S5 1 G m2 S6 C1 C2 • The Gm2 compensation circuit is not in the signal path. The original frequency/speed performance can be maintained. Comparators 18-36 Analog ICs; Jieh-Tsorng Wu Operational Amplifier with Offset Compensation During the reset mode (φ1 = 1) Vo = VOS 1 · Gm1R + (VOS 2 − Vo) · Gm2 R ⇒ Vo = VOS 1 · Gm1R + VOS 2 · Gm2R 1 + Gm2R ⇒ Vo ≈ VOS 1 · Gm1 + VOS 2 Gm2 If Gm2R 1 • VOS 1 and VOS 2 are the input-referred offset of the Gm1-R and Gm2-R pairs. During the amplification mode (φ2 = 1) VOS 2 VOS 1 Gm2 Gm1 + + ∆V + VOS 2 + ∆V · Gm2R = Gm1 R Vi + Vo = Vi · Gm1R + VOS 1 Gm2 Gm2R Gm1R Gm1 Input-Referred Offset = VOS,i n VOS 1 VOS 2 Gm2 + + ∆V · = Gm2R Gm1R Gm1 • ∆V is due to the mismatch between the switching errors of S5 and S6. Its effect on Vo can be reduced by making Gm2/Gm1 small. Comparators 18-37 Analog ICs; Jieh-Tsorng Wu Operational Amplifier with Offset Compensation VDD M9 M10 M3 M4 Vi1 Vi2 2 1 VBP1 VBP2 Vo1 S3 M1 S1 2 Vo2 M2 M6 M5 VBN2 S2 1 S4 1 S5 C1 I1 M8 M7 VBN1 1 M11 M12 S6 C2 I2 VSS Comparators 18-38 Analog ICs; Jieh-Tsorng Wu The Chopper Stabilization Technique 1 1 fc Vi VOS 0 Vo A f 0 LPF 1 f f 0 f fc 0 f fc 0 f • The bandwidth of the amplifier A must be wider than fc. • The amplifier A should employ design of minimizing thermal noise. Comparators 18-39 Analog ICs; Jieh-Tsorng Wu A Chopper Operational Amplifier VDD R1 R2 I3 φ I4 I5 M5 M6 C1 M3 φ 1 M4 Vo C2 Vi M1 RL M2 Vi I1 M7 I2 M8 M9 VSS φ a φa b b a Comparators φb 18-40 Analog ICs; Jieh-Tsorng Wu A Chopper Operational Amplifier • The M1–M2 is a low-gain low-noise stage. • The M3–M4 is a high-gain stage with low Gm. A common-mode feedback circuit is required to stabilize the drain voltages of M3 and M4. • The M5–M8 is a high-gain Miller stage for frequency compensation and low-pass filter. • The M9 is a low-gain buffer stage. • The chopper can introduce additional kT /C noise. • Reference: A. Bakker, et al., “A CMOS Nested-Chopper Instrumentation Amplifier with 100-nV Offset,” JSSC 12/2000, pp. 1877–1883. • Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization,” Proc. IEEE, 11/1996, pp. 1584–1614. Comparators 18-41 Analog ICs; Jieh-Tsorng Wu Residual Offset of Chopper Amplifier 1 1 fc Vi Vo A VOS LPF 1 f t Modulation Signal t Spikes at Input t Demodulation Signal Residual Offset t Comparators 18-42 Demodulated Spikes Analog ICs; Jieh-Tsorng Wu Chopper Modulation with Guard Time 1 1 fc Vi Vo A VOS LPF 1 f t Modulation Signal t Spikes at Input t Demodulation Signal Residual Offset t Comparators 18-43 Demodulated Spikes Analog ICs; Jieh-Tsorng Wu Chopper Modulation with Guard Time • The spikes at the input is due to the switching error mismatch of the chopper. • The residual offset is linear dependent on chopper frequency. √ • Reference: Q. Huang and C. Menolfi, “A 200nV Offset 6.5nV/ Hz Noise PSD 5.6kHz Chopper Instrumentation Amplifier,”, ISSCC 2002. Comparators 18-44 Analog ICs; Jieh-Tsorng Wu Oscillators Jieh-Tsorng Wu ES A October 16, 2002 1896 National Chiao-Tung University Department of Electronics Engineering The Barkhausen Criteria Se Si a S fb So = a · Se Closed-Loop Gain = A ≡ f Sf b = f · So So Si = So Se = Si − Sf b a a = 1 + af 1+T Loop Gain = T ≡ a × f The feedback system oscillates at ωo, if |T (j ωo)| ≥ 1 OSCs ∠T (j ωo) = 180◦ 19-2 Analog ICs; Jieh-Tsorng Wu Three-Stage Ring Oscillator VDD VDD R V1 VDD R V1 R V2 V3 V2 C C C V3 t gm R −T (s) = − 1 + sRC 3 3 =− A0 s 1+ω 3 A0 = gmR 1 ωp = RC p OSCs 19-3 Analog ICs; Jieh-Tsorng Wu Three-Stage Ring Oscillator From the Barkhausen criteria, −1 tan ωo ωp = 60◦ ⇒ ωo = 3ωp 3 A0 1+ ωo ωp 2 3 =1 ⇒ A0 = gmR = 2 ◦ ◦ ◦ • The phase difference between the neighboring nodes is 180 + 60 = 240 . • If A0 > 2, the oscillation amplitude increase exponentially until nonlinear effect limits the growth. A0 A0 − 2 ωpt cos ωot V (t ) ∝ exp 2 2 OSCs 19-4 Analog ICs; Jieh-Tsorng Wu Three-Stage CMOS Inverter Ring Oscillator VDD VD D V1 V2 V3 GND t 1 fo = 6tp Req = 1 1 t 0.69ReqnC + 0.69ReqpC tp = + tpLH = 2 pHL 2 −1 VDD /2 VDD /2 VDD 3 VDD V dV ≈ 4 IDSAT IDSAT (1...
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