Analog Integrated Circuits (Jieh Tsorng Wu)

Active rc filters capacitor integrators active rc

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Unformatted text preview: ivity Transfer Function Sensitivity Second-Order Filter Sensitivity High-Order Filter Sensitivity 21. Active-RC Filters Capacitor Integrators Active-RC Inverting Integrators Actively Compensated Inverting Integrator Noninverting Integrator Phase-Lead Noninverting Integrator Band-Reject Filter Specifications First-Order Filters Second-Order Filter (Biquadratic Function) Second-Order Low-Pass (LP) Filter Single-Amplifier 2nd-Order Filters -SallenKey LP Biquad Second-Order High-Pass (HP) Filter State-Variable Second-Order Filters Second-Order Band-Pass (BP) Filter Tow-Thomas (TT) Biquad Ackerberg-Mossberg (AM) Biquad Arbitrary Transmission Zeros by Summing Arbitrary Transmission Zeros by Voltage Feedforward MOST Transconductors with Source Degeneration BJT Transconductors Multi-Input Transconductors High-Order Filter Using Cascade Topology Transconductor’s Imperfections Cascaded Filter Design Procedures High-Order Filter Using the Follow-theLeader Feedback Topology High-Order Filter LC Ladder Simulation The Effect of Non-Zero go on Gyrators The Effect of Phase Shift on Gyrators Gm-C First-Order Filters LC Ladder Simulation Gm-C Second-Order Filters An All-Pole Low-Pass Ladder Filter Signal-Level Scaling in Ladder Filters Gm-C First-Oder Filters Using Miller Integrators General Ladder Branches General Ladder Branches by Active-RC Implementation Finite Transmission Zeros in the Series Branches 22. MOST-C and Gm-C Filters MOSTs in the Triode Region MOST-C Fully-Balanced Integrators Gm-C Second-Oder Filters Using Miller Integrators Ladder Filter Using Simulated Gyrators Ladder Filter Using Signal-Flow Graph Gm-C Simulation of Ladder Branches (I) Gm-C Simulation of Ladder Branches (II) Gm-C Resonators Double MOST-C Differential Integrators R-MOST-C Differential Integrators A MOST-C Tow-Thomas Biquad Gm-C Quadrature Oscillators On-Chip Tuning Strategies Transconductors Separate Frequency and Q Control Transconductor Basic Circuits Gm Tuning Gm-C Lossy Integrator Frequency Tuning Using Switched Capacitors Fully-Differential Gm-C Integrators Frequency Tuning Using Response Detection Gm-C Opamp Integrators (Miller Integrators) Gyrators Gm-C Simulated Gyrators MOST Transconductors Frequency Tuning Using Phase-Locked Loop Q-Factor Tuning Using MLL Q-Factor Tuning Using LMS 23. Switched-Capacitor Filters Time-Staggered SC Stages Switched-Capacitor Equivalent Resistor Capacitor Scaling Switched-Capacitor Integrators Output Capacitor Scaling SC Integrator Analysis Input Capacitor Scaling SC Differential Integrators An All-Pole Low-Pass Ladder Filter Effects of Parasitic Capacitances An All-Pole Low-Pass SC Ladder Filter Parasitics-Insensitive SC Integrators SC Ladder Filter Using Signal-Flow Graph Fully Differential SC Integrators SC Ladder Filters Design Methodology MOST Analog Switches SC Ladder Filters Design Procedures Effects of Opamp’s Finite DC Gain 24. Niquist-Rate Digital-to-Analog Converters Effects of Opamp’s DC Offset An Offset Auto-Zeroing Scheme Effects of Opamp’s Finite Settling Time An SC Integrator with CDS A/D and D/A Interfaces Continuous-to-Discrete Conversion Discrete-to-Continuous Conversion Discrete-Time Signal Processing Imperfections in Discrete-to-Continuous Conversion Continuous-Time Signals D/A Transfer Characteristic Discrete-Time Signals D/A Nonlinearity s-to-z Transformation D/A Performance Metrics - Static Characteristics Bilinear s-to-z Transformation Hc(s) to H(z) Design Procedures for Bilinear Transformation Switched-Capacitor Filter Systems Design Constraints Periodic Time-Variance in Biphase SC Filters Active Switched-Capacitor Integrators SC First-Order Filters Switch Sharing D/A Performance Metrics - Dynamic Characteristics Dynamic Range Resistor-String DACs with Digital Decoding Folded R-String DACs with Digital Decoding R-String DACs with Binary-Tree Decoding Intermeshed Resistor-String DACs (OneLevel Multiplexing) Bilinear SC First-Order Filters Intermeshed Resistor-String DACs (TwoLevel Multiplexing) SC Second-Order Filters Binary-Weighted Current-Steering DACs A Low-Q SC Biquad Binary-Weighted R-2R Networks A High-Q SC Biquad Equally-Weighted Current-Steering DACs The Matrix Floorplan A Current Cell Example Digital Encoding for Feedforward Architecture the Quantized- Charge-Redistribution DACs A Radix-2 1ff5 Bit SC Pipeline Stage Segmented DAC Architecture Multi-Bit Switched-Capacitor Pipeline Stage A 10-Bit Segmented Current-Steering DAC Switched-Capacitor Pipelined ADCs A Segmented Current-Steering DAC Single-Stage Calibration and Digital Correction Dynamically-Matched Current Sources A Segmented Charge-Redistribution DAC A Capacitor-Resistor Hybrid DAC 25. Niquist-Rate Analog-to-Digital Converters A/D and D/A Interfaces Continuous-to-Discrete Conversion Multi-Stage Calibration and Digital Correction Calibration of A Radix-2 1ff5 Bit SC Pipeline Stage A Radix-2 Cyclic ADCs A Radix-2 Switched-Capacitor Cyclic ADC A/D Quantization Characteristic Imperfections in A/D Quantization Characteristic Quantization Noise Sampling-Time Uncertainty (Aperture Jitter) A CMOS Subranging Flash ADC - Dingwall A CMOS Subranging Flash ADC - Brandt Interpolated Differential Comparator Bank A CMOS Subranging Flash ADC - Brandt DFT Nonlinearity Test of ADCs Code Density Test of ADCs Flash Quantization Architecture Serial (Integrating) Architectures Resistor-String Interpolation Parallel (Flash) Architectures Folding Successive Approximation Architectures Interpolation and...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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