Analog Integrated Circuits (Jieh Tsorng Wu)

Careful layout is required fully dierential circuit

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Unformatted text preview: (W/L)7 • Further, to minimize process induced variations choose L3 = L4 = L6 However, this constraint may conflict with frequency response and noise constraints. Opamp-I 13-25 Analog ICs; Jieh-Tsorng Wu Random Input Offset Voltage ∆Vi −j = |Vi | − |Vj | ∆ W L = i −j ⇒ −VOS,r = ∆Vt,1−2 + = ∆Vt,1−2 − Vi −j = W L i ∆ID,3−4 = W L j ∆(W/L)3−4 (W/L)3−4 Vov,1−2 ∆ID,1−2 2 Vov,1−2 Vov,3−4 ∆Ii −j = |Ii | − |Ij | 2 W L − ID,3−4 |Vi | + |Vj | ID,1−2 − · ∆Vt,3−4 + = i −j −2 W L 1 2 ∆Vt,3−4 Vov,3−4 Ii −j = = W L + i |Ii | + |Ij | 2 j ∆ID,1−2 ID,1−2 ∆(W/L)1−2 (W/L)1−2 Vov,1−2 2 − ∆(W/L)1−2 (W/L)1−2 + ∆(W/L)3−4 (W/L)3−4 Vov,1−2 ∆(W/L)1−2 ∆(W/L)3−4 gm3 − · ∆Vt,3−4 + + = ∆Vt,1−2 − gm1 2 (W/L)1−2 (W/L)3−4 Opamp-I 13-26 Analog ICs; Jieh-Tsorng Wu Input Offset Voltage and Common-Mode Rejection Ratio The output voltage change due to common-mode input variation is ∆Vo = Acm · ∆Vi c Want to change differential input so that ∆Vo = 0, then ∆Vi d ∆Vo Acm =− =− · ∆Vi c Ad m Ad m Therefore, we have CMRR ≡ Opamp-I Ad m Acm = −1 ∂ Vi d ∂Vi c = ∆V o = 0 13-27 ∂ VOS −1 ∂Vi c Analog ICs; Jieh-Tsorng Wu CMRR Due to Systematic and Random Offset Since VOS = VOS,s + VOS,r We have ∂ VOS,s ∂VOS,r 1 + = ∂Vi c ∂Vi c CMRR ∂ VOS,s ∂Vi c ∂VOS,s ∂Vov 1 ∂Id 1 gm1 1 1 = · · = − (λ1 + λ3)(VY − V1) · · gm1 1 + 2(gm1 + gmb1)ro5 2 ∂Vov 1 ∂Id 1 ∂Vi c (λ1 + λ3)(VY − V1) 1 1 = − (λ1 + λ3)(VY − V1) · ≈− 2 1 + 2(gm1 + gmb1)ro5 4(gm1 + gmb1)ro5 ∂VOS,r ∂Vi c ∂VOS,r ∂Vov 1 ∂Id 1 ∆(W/L)1−2 ∆(W/L)3−4 1 1 − · = · · =− + 2 ∂Vov 1 ∂Id 1 ∂Vi c 1 + 2(gm1 + gmb1)ro5 (W/L)1−2 (W/L)3−4 =− − Opamp-I ∆(W/L)1−2 (W/L)1−2 13-28 + ∆(W/L)3−4 (W/L)3−4 · 1 4(gm1 + gmb1)ro5 Analog ICs; Jieh-Tsorng Wu Mismatches and Input Stage Transconductance Define ∆gm,i −j = gm,i − gm,j gm,i −j = gm,i + gm,j 2 ∆ro,i −j = ro,i − ro,j ro,i −j = ro,i + ro,j 2 Then Gmd ≈ gm,1−2 · 1− ∆gm,1−2 2 2gm,1−2 1+ ∆gm,3−4 2gm,3−4 Gmc ≈ − gm,1−2 1 + 2gm,1−2ro5 ·( d + m) where d m Opamp-I ∆gm,1−2 2ro5 2ro5 ∆ro,1−2 1 1+ − ≈ − · gm3ro1 gm,1−2 ro1 ro1 ro,1−2 ∆gm,3−4 (gm3 − gm4)ro3 1 1 = + ≈ + gm3ro3 gm,3−4 1 + gm3ro3 1 + gm3ro3 13-29 Analog ICs; Jieh-Tsorng Wu Power Supply Rejection Ratio (PSRR) VDD vo = −Av vi d + Ad d vd d + Ass vss vdd VDD M3 PSRRDD PSRRSS M4 M6 vid M1 VB1 Cc M2 VSS Av (0) 1 − s/p1 Av (0) = gm1gm6R1R2 gm1 Av (0)p1 = − Cc gm1 Av ≈ for ω |p1| sCc vss VSS Opamp-I Av ≡ Ass Av = Vo M7 M5 Av ≡ Ad d 13-30 Analog ICs; Jieh-Tsorng Wu Power Supply Rejection Ratio (PSRRSS) VDD M3 M4 vo Av = Av,cm = vss1 CMRR 1 Z6 ≈ gm6 M6 Cc M1 x r x Z v o M2 C x r o7 v ss1 VSS 6 C 1 Z7 = go7 + sC7 7 Z6 Z6 go7 + sC7 vo = ≈ ≈ vss2 Z6 + Z7 Z7 gm6 v ss2 VSS vo/vss1 + vo/vss2 (1 + sro7 C7)(1 − s/p1 ) 1 1 1 = = ≈ + Av gm6ro7Av (0) PSRRSS CMRR CMRR Opamp-I 13-31 Analog ICs; Jieh-Tsorng Wu Power Supply Rejection Ratio (PSRRDD) v dd2 M3 M4 y g v dd1 1 v 1 M6 v dd2 v y Cc M1 x C v o M2 C y m4 (vdd2 - v y ) g m3 v y y0 R R y0 1 Cc v o R 2 M5 VB1 M7 VSS v dd1 R 1d v 1 C 1d Cc g g v dd1 v o v o m6 R R Opamp-I m6 (vdd1 - v 1 ) 2 2 13-32 Analog ICs; Jieh-Tsorng Wu Power Supply Rejection Ratio (PSRRDD) The voltage gain from vd d 1 to vo is vo vd d 1 = 1 1+ 1+(g1d +sC1d )/(sCc ) R2 (g1d +sC1d )+gm6R2 ≈ 1 1+ C1d /Cc g m6 R 2 ≈1 Gy 0 + sCy 0 , the resulting current flow in M3 is For vd d 2 input, since gm3 + sCy approximately iy 0 ≈ vd d 2 · (gy 0 + sCy 0 ) The current is mirrored in M4, and amplified by M6 and Cc. The voltage gain is gy 0 + sCy 0 vo = iy 0 · Av 2 ≈ − vd d 2 sCc Thus PSRRDD ≈ Opamp-I Av vo/vd d 1 13-33 ⇒ vo vo vd d 2 vd d 1 ≈ Av Analog ICs; Jieh-Tsorng Wu PSRRDD with Common-Gate Miller Compensation M3 M4 y v 1 v y Bias v dd1 R M6 1 M1 g v dd1 m6 (vdd1 − v1 ) 1d M10 x M2 C v dd1 Cc m6 Cp v 1 v o g 1d v o R 2 M10 Cp M10 M5 Cc M7 Cc v o R 2 VSS Assume the M10 stage has Ri n = 1/gm10 and AI = 1. Neglecting R1d and C1d , we have vo vd d 1 Opamp-I = 1 1 1+sCc/gm10 · Cc Cp sCc +g m6 +g 13-34 1 m6 R 2 ≈ Cp Cc · 1+s Cc gm10 Analog ICs; Jieh-Tsorng Wu Supply Capacitance CI VDD CI M3 Csup M4 Cgd1 Vy Vo Vn M1 Vo = − Csup CI Cgs1 · Vn M6 VB1 Id5 Vx M2 Cc Vo M5 M7 VSS • Both Cgs1 and Cgd 1 can function as Csup, and noises at Vx and Vy can leak to the output. Opamp-I 13-35 Analog ICs; Jieh-Tsorng Wu Power-Supply Rejection and Supply Capacitance • The VDD noise can be coupled to Vy through the diode-connected M3 device. The use of cascode input stage can overcome this problem. • If Id 5 is modulated by the supply voltage variation, then vx ≈ id 5/(2gm1). The use of supply-independent bias reference can overcome this problem. • The noises at the substrate/well terminals of M1 and M2 can change the Vt of the devices due to body effect, and cause Vgs variation, introducing no...
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