Analog Integrated Circuits (Jieh Tsorng Wu)

Comparators 18 24 analog ics jieh tsorng wu most

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Unformatted text preview: nded by Ao. • It is faster than the multi-stage cascaded amplifier, and dissipates less power. • Require a strobe signal (clock). • Let Tc be the conversion time, the final output Vo(Tc) = V , and the initial sampled input Vo(0) has a uniform distribution between −V and +V . Then the probability of observing a metastable state is T (A −1)T V/U −c 1 − oRC c = =e ≈ e C/gm P= V U The metastable state occurs when the sampled input is so small that the regenerated output, |Vo|, cannot reach |V | after the Tc period. Comparators 18-7 Analog ICs; Jieh-Tsorng Wu Output Offset Storage (OOS) V V 2 i S1 1 A S2 C V OS V c o o Latch Q 1a S3 C L V’ o V OSL During the reset mode (φ1 = 1) Vo = 0 Vc = A × VOS During the amplification mode (φ2 = 1) Co ∆Q ∆Q VOSL Co + CL Vi + · + − VOSL = A · − Vo = Vi × A · Co + CL Co + CL Co + CL ACo A Co Co Input-Referred Offset = VOS,i n Comparators 1 ∆Q VOSL Co + CL · =· − A Co A Co 18-8 Analog ICs; Jieh-Tsorng Wu Output Offset Storage (OOS) • During the reset-to-amplification transition, let S3 open before S2, so that ∆Q can be a constant. • Amplifier A cannot employ high gain. • Amplifier A must cover the input common-mode range. • Want latch with high-impedance (capacitive) input so as not to discharge Co during amplification. • Make Co Comparators CL to avoid attenuation. 18-9 Analog ICs; Jieh-Tsorng Wu Multistage Output Offset Storage V S1 V V c1 X V c2 Y c3 V i A1 C A2 1 V OS1 C A3 2 V OS2 S2 C o 3 V OS3 S3 S4 S5 S1 S2 S3 S4 S5 I Comparators II III 18-10 IV V Analog ICs; Jieh-Tsorng Wu Multistage Output Offset Storage During Period I, S1 open, S2–S5 closed. Vc1 = A1VOS 1 Vc2 = A2VOS 2 Vc3 = A3VOS 3 During Period II, S3 open. VX = 2 = S3 Switching Error Vc1 = A1VOS 1 + Vc2 = A2(VOS 2 − 2 2) During Period III, S4 open. VY = 3 = S4 Switching Error Vc2 = A2(VOS 2 − 2) + Vc3 = A3(VOS 3 − 3 3) During Period IV, S5 open. Vo = Comparators 4 = S5 Switching Error 18-11 Vc3 = A3(VOS 3 − 3) + 4 Analog ICs; Jieh-Tsorng Wu Multistage Output Offset Storage During Period V (amplification mode), S2 closed, S1 open. Vo = A1 · A2 · A3 · Vi + VOS,i n = Comparators 4 4 A1 · A2 · A3 18-12 Analog ICs; Jieh-Tsorng Wu Input Offset Storage (IOS) Q V V 2 i S1 1 S2 1a S3 c V o Latch Ci A C V OS L V’ o V OSL During the reset mode (φ1 = 1) Vo = Vc = VOS × A A+1 During the amplification mode (φ2 = 1) VOS ∆Q ∆Q VOSL A − + A − VOSL = −A Vi − + Vo = −Vi × A + VOS A + 1 Ci A + 1 Ci A Input-Referred Offset = VOS,i n Comparators 18-13 VOS ∆Q VOSL + =− + A + 1 Ci A Analog ICs; Jieh-Tsorng Wu Input Offset Storage (IOS) • The S3 switching error ∆Q is input-independent. • During the reset-to-amplification transition, let S3 open before S2. • The IOS allows rail-to-rail input common-mode level and quick overdrive recovery. • Amplifier A can employs high gain. • Amplifier A may require compensation Cc to ensure closed-looped stability. Cc can be switched off during the amplification mode. Comparators 18-14 Analog ICs; Jieh-Tsorng Wu Multistage Input Offset Storage V S3 V c1 S1 S4 V c2 V i C 1 A1 C 2 X o A2 V OS2 V OS1 S2 S1 S2 S3 S4 I Comparators II 18-15 III IV Analog ICs; Jieh-Tsorng Wu Multistage Input Offset Storage During Period I, S1 open, S2–S4 closed. Vc1 A1 VOS 1 = A1 + 1 Vc2 A2 A2 A1 VOS 2 − Vc1 = VOS 2 − VOS 1 = A2 + 1 A2 + 1 A1 + 1 During Period region II, S3 open. Let A1 VOS 1 + A1 + 1 1 During Period III, S4 open. Let 2 Vc1 = Vc2 Comparators 1 be the 3 switching error. Vc2 = A2 A1 VOS 2 − VOS 1 + A1 A2 + 1 A1 + 1 1 be the S4 switching error. A2 A1 V V = − + A1 A2 + 1 OS 2 A1 + 1 OS 1 1 18-16 + 2 A2 V Vo = − A2 A2 + 1 OS 2 2 Analog ICs; Jieh-Tsorng Wu Multistage Input Offset Storage During Period IV (amplification mode), S2 open, S1 closed. A2 VOS 2 − A2 Vo = A1A2Vi + A2 + 1 2 = A1A2 Vi + Input-Referred Offset = VOS,i n = Comparators 18-17 VOS 2 A1 (A2 + 1) VOS 2 A1(A2 + 1) − − 2 A1 2 A1 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Auto-Zeroing Inverter VDD V V V o 2 i1 1 i2 X S1 C I MA 1 V S3 o MB S2 V VSS Comparators Bias Point 18-18 x Analog ICs; Jieh-Tsorng Wu MOST Comparator: Auto-Zeroing Inverter • Trade-off between speed and resolution by selecting different value of C. • Very sensitive to supply noises. • Power dissipation is strongly process- and supply-dependent. • Kickback noise presented at the inputs. • Reference: T. Kumamoto, et. al., JSSC, 12/86, pp. 976–982. Comparators 18-19 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Cascaded Auto-Zeroing Inverters VDD V V i1 M1 M3 S1 Latch C i2 VDD 1 S3 C 2 M2 Vo S4 M4 S2 VSS VSS CK S1 S2 S3 S4 CK Comparators 18-20 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Preamp + Regenerative Sense Amplifier VDD M3 M5 M4 M6 Vo V i1 M1 M2 V i2 M7 I1 VSS Comparators VDD M8 M11 VSS 18-21 M9 φ M10 M12 VSS Analog ICs; Jieh-Tsorng Wu MOST Comparator: Preamp + Regenerative Sense Amplifier • During the track mode (φ = 1), want gm7,m8 < gm9,m10 so that the combination of M7-M8 and M9-M10 pair become the resistive loa...
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