Analog Integrated Circuits (Jieh Tsorng Wu)

During the amplication mode 2 1 vos 2 vos 1 gm2 gm1

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ds for M5 and M6. The small-signal voltage gain is (W/L)6 vo gm1 ≈ · vi gm9 − gm7 (W/L)4 • During the latch mode (φ = 0), M7, M8, and M11 must be large enough to prevent the change of latched state by the Vi variation. • All nodes are low impedance, thus giving fast operation. • Overdrive recovery can be improved by adding an equalizing switch between the Vo nodes. • The preamplifier buffers the kickback from the input circuitry. • Reference: B. Song, et al., JSSC, 12/90, pp. 1328–1338. Comparators 18-22 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Preamp + Regenerative Sense Amplifier VDD VDD φ M3 M13 M5 M4 M6 M11 M12 IVT1 A Vo V i1 M1 M2 B IVT2 V i2 M8 φ M7 M9 M10 I1 VSS Comparators VSS VSS 18-23 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Preamp + Regenerative Sense Amplifier • During the track mode (φ = 1), need M7 and M8 large enough to overpower the M9M10 cross-coupled pair and pull VA and VB below the input threshold level of IVT1 and IVT2. • During the latch mode (φ = 0), the M9-M10 and M11-M12 pairs provide regeneration. They must be large enough to to prevent the change of latched state by the Vi variation. The input threshold level of IVT1 and IVT2 must be high enough to avoid false triggering. Comparators 18-24 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Merged Preamp + Sense Amplifier VDD CK M6 M8 M5 M7 M9 M10 M4 M1 when CK • Kickback noise is generated at input during the 0-to-1 transition of CK. M2 Vi CK dissipation • When CK=1, the M1-M2 pair is activated first, the M3-M4 pair is second, and the M5-M6 pair is the last. Vo M3 • No power CK=0. • Reference: B. Razavi, 1999 ISSCC Short Course. M11 VSS Comparators 18-25 Analog ICs; Jieh-Tsorng Wu Offset Canceled Latches: Idea C1 S1 Vi 1 S3 R L1 S5 Vo 2 S2 1 S4 1 G m2 G m1 S6 R L2 C2 • During reset mode (φ1 = 1), the OOS is applied to both Gm1 and Gm2. • During reset mode, the finite on-resistance of S5 and S6 may cause oscillation. • During reset-to-regeneration transition, any mismatch of the switching errors between S5 and S6 can trigger a false regeneration, yielding a large input-referred offset. Comparators 18-26 Analog ICs; Jieh-Tsorng Wu Offset Canceled Latches: Simplified Schematic B1 S1 Vi 1 S3 R L1 2a 2 S9 1 S5 Vo S2 1 S4 G m1 G m2 R L2 B2 Comparators 1 S7 C1 18-27 C2 2 S10 1 S6 1 S8 Analog ICs; Jieh-Tsorng Wu Offset Canceled Latches: Simplified Schematic • During reset mode, the positive feedback loop is completely broken. • The regeneration begins only after Vi has been sensed and amplified. • Buffers B1 and B2 isolate output nodes from C1 and C2, thus enhancing regeneration speed. • The residual offset is primarily cause by the switching errors of S5–S10. • Reference: B. Razavi, et al., “Design Techniques for High-Speed High-Resolution Comparators,” JSSC, 12/92, pp. 1916–1926. Comparators 18-28 Analog ICs; Jieh-Tsorng Wu Offset Canceled Latches: MOST Implementation VDD M7 M5 M6 M8 M9 M10 C1 V o+ A C MS9 E F M3 MS7 I3 B MS10 D M4 MS5 C2 V oMS8 I4 MS6 VSS VSS φ1 V B1 φ2 I2 VSS V B1 φ1 φ1 MS1 V 1+ MS2 M1 V 2+ V 2- MS4 I1 φ1 φ1 V 1- M2 MS3 φ2 φ1 VSS Comparators 18-29 Analog ICs; Jieh-Tsorng Wu Offset Canceled Latches: MOST Implementation • M7 and M8 are active loads, which both decrease the voltage drops across M5 and M6, increase available gain, increase Vo output swing, and enhance speed. d • An equalizing switch driven by φ1 can be placed between node C and D to eliminate the switching error mismatch between MS7 and MS8. d • An equalizing switch driven by φ2 can be placed between node E and F to eliminate the mismatch between MS5 and MS6. In this case, MS9 and MS10 are driven by dd φ2 and the charge absorption mismatch between MS9 and MS10 becomes the only significant contribution to the offset, which is VOS (i n) ∆Q gm3 + gm7 · = gm1 C • Reference: B. Razavi, JSSC, 12/92, pp. 1916–1926. Comparators 18-30 Analog ICs; Jieh-Tsorng Wu BJT Latched Comparator VCC R1 R2 Q7 Q8 Q1 Q2 Q3 Q4 Vo Vi Q5 Q6 φ I1 I2 I3 VEE Comparators 18-31 Analog ICs; Jieh-Tsorng Wu BJT Latched Comparator • During the track mode (φ = 1), the variation of input capacitance with Vi causes input-dependent delay and hence harmonic distortion. • Speed may be limited by overdrive recovery. • During latch-to-track transition, Q1 and Q2 are initially off, the I1 current then flows through Q5 and the emitter junctions of Q1 and Q2 to the input, creating kickback noise. • Usually preceded by a buffer. Comparators 18-32 Analog ICs; Jieh-Tsorng Wu BJT Comparator with High-Level Latch VCC R1 R2 Vo Q3 • During the latch mode (φ = 0), the variation in Vi will not disturb the latched state. • Q1 and Q2 are never turned off, thus reducing kickback noise. Q4 Q5 φ Q6 B A Q1 Q2 Vi Q7 Q8 φ • The kickback noise results only from the transients at nodes A and B. Adding a resistor between A and B decreases these transient and improves the recovery at these node. I1 VEE Comparators 18-33 Analog ICs; Jieh-Tsorng Wu A Sampled-Data Amplifier with Internal O...
View Full Document

This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

Ask a homework question - tutors are online