Unformatted text preview: nce de · sv = −de · sv , we can add [1] to sy at any time.
• The ﬁrstorder algorithm is similar to the dataweighted averaging algorithm.
Oversampling 2647 Analog ICs; JiehTsorng Wu General MismatchShaping DAC — SecondOrder Example
H2(z ) = 1 − z −1 M=4
sv(k ) = VQ[sy(k )]
k
0
1
2
3
4
5
6 Oversampling v (k )
1
1
1
2
0
4
2 se(k ) = sv(k ) − sy(k )
sy(k )
1, 1, 1, 1
0, 2, 2, 2
0, 1, 3, 3
0, 1, 2, 4
0, 1, 0, 3
1, 2, 0, 4
2, 3, 0, 5 sv(k )
1, 0, 0, 0
0, 1, 0, 0
0, 0, 1, 0
0, 0, 1, 1
0, 0, 0, 0
1, 1, 1, 1
0, 1, 0, 1 sx(k ) = −2se(k − 1) + se(k − 2) se(k )
+0, −1, −1, −1
+0, −1, −2, −2
+0, −1, −2, −3
+0, −1, −1, −3
+0, −1, +0, −3
+0, −1, +1, −3
−2, −2, +0, −4 2648 2 sx(k )
−0, +2, +2, +2
−0, +1, +3, +3
−0, +1, +2, +4
−0, +1, +0, +3
−0, +1, −1, +3
−0, +1, −2, +3
+4, +3, +1, +5 Analog ICs; JiehTsorng Wu General MismatchShaping DAC — SecondOrder Example
• The element selection logic (ESL) is stable, i.e, se is bounded, for H2(z ) = 1 − z
as long as v stays away from the extremes of its range. −1 2 , • When a binary modulator is unstable with an NT F (z ) equal to H2(z ), the corresponding
ESL algorithm must also be unstable.
• Adding dither to sy may be necessary to whiten the noise caused by a deterministic
selection algorithm. Oversampling 2649 Analog ICs; JiehTsorng Wu MultiBit Unit Elements
• If polarity reversal or repeated use of an unit element in one period is allowed, the
components of sv need not be restricted to {0, 1}.
• Multibit can enhance the stability of the ESL in the same manner that multibit
feedback enhances the stability of a regular ∆Σ modulator.
• The key circuit constraint is the need to ensure that each usage of an element results
in the same error. Oversampling 2650 Analog ICs; JiehTsorng Wu Decimation and Interpolation
Decimation
w(n) x(n)
h(n)
fs Xe f s /M fs π 2π 0 π 2π 2M π π 2π 2π /L 2π ω jω ω
0 π/L 0 π/L Y ej ω 2π Lfs jω 0 We π/M Lfs ω jω y(m) h(n) L Xe Y ej ω Oversampling x(n) jω 0 Interpolation
w(m) M
fs 0 We y(m) ω
2651 2π ω ω Analog ICs; JiehTsorng Wu Decimation and Interpolation
∞ Decimation Filter = y (m) = h(k )x (Mm − k )
k =−∞
∞ Interpolation Filter = y (m) = h(m − kL)x (k )
k =−∞ • The processes of decimation and interpolation are in eﬀect duals.
• A ﬁlter deﬁned for one process can often be used for other if the same parameters
are used.
• An architecture that is eﬃciently deﬁned for one process can often be transposed for
used as an eﬃcient architecture in the dual process. Oversampling 2652 Analog ICs; JiehTsorng Wu MultiStage Rate Conversion
x(n) y(m) LPF 64 N 2822.4 kHz 44.1 kHz
1+ δ 1
1− δ 1
kHz 20 22.05 1411.2 δ2 ω x(n) LPF 2822.4 kHz 88.2 kHz π
y(m) LPF 32 N1 ωs ωp 0 2 N2 44.1 kHz 44.1
kHz
20 Oversampling 66.15 1411.2 kHz
20 22.05 2653 Analog ICs; JiehTsorng Wu MultiStage Rate Conversion
• The order N of an equiripple FIR ﬁlter is
2
−10 log10(δ1 δ2) − 13
f (δ1, δ2) − g(δ1, δ2)(∆ω)
≈
N≈
∆ω
14.6∆ω
2
2
f (δ1, δ2) = (0.005309x1 + 0.07114x1 − 0.4761)x2 − (0.00266x1 + 0.5941x1 + 0.4278) g(δ1, δ2) = 11.012 + 0.51244(x1 − x2)
ωs − ωp
x1 = log10 δ1
x2 = log10 δ2
∆ω =
2π
• For the singlestage design, δ1 = 0.001, δ2 = 0.00001, then N = 6250. For the
twostage design, δ1 = 0.001/2, δ2 = 0.00001, then N1 = 291 and N2 = 205.
• Practical considerations sometimes lead to the conclusion that a twostage design is
best.
• For most cases, the choice of 2 : 1 for the last stage is both the theoretically best
option as well as the most practical one.
Oversampling 2654 Analog ICs; JiehTsorng Wu sinck Filters
1
x(n)
z fs 1 2
z M−1 1 z 1
y(m)
M f s /M sinc
1 0 x(n) 2π /M 4π /M 8π /M ω π sinc sinc 1 2 y(m) sinc
k fs M f s /M x(n) y(m) fs
z 1 z 1 z M z M M f s /M x(n)
y(m) fs
z Oversampling 1 z 1 M
z 2655 1 z 1 f s /M Analog ICs; JiehTsorng Wu sinck Filters
The sinc ﬁlter transfer function is
1
H1(z ) =
M
H1 e jω M −1 z −1 i =0 1
=
M 1 sin(ωM/2) sinc(ωM/2)
·
=
=
M sin(ω/2)
sinc(ω/2) −M 1−z
1 − z −1 sin(x )
sinc(x ) =
x k The sinc ﬁlter transfer function is
1
H (z ) = [H1(z )]k =
Mk −M 1−z
1 − z −1 k 1
1
=
·
1 − z −1
Mk k · 1 − z −M k • The integratordiﬀerentiator architecture is inherently stable, when 2’scomplement
arithmetic is used due to its wraparound characteristic. Oversampling 2656 Analog ICs; JiehTsorng Wu PhaseLocked Loops JiehTsorng Wu ES A July 16, 2002 1896 National ChiaoTung University
Department of Electronics Engineering PhaseLocked Loops (PLLs) Ai Phase
Detector Ai = g1 (ωi t + θi ) Loop
Filter Ao = g2 (ωot + θo) Vc VFO
Ao ωo = ωoo + Kc · Vc • g1 and g2 are periodic functions with 2π period.
• When the loop is locked, the frequency of the VCO is exactly equal to the average
frequency of the input.
• The loop ﬁlter is a lowpass ﬁlter that suppresses high...
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 Winter '09
 Choma
 Integrated Circuit, Transistor, The Land, Bipolar junction transistor, VDS, Analog ICs, JiehTsorng Wu

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