Analog Integrated Circuits (Jieh Tsorng Wu)

For a sinusoidal pd p o 18n 1 plls 27 21 for 05

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Unformatted text preview: nce de · sv = −de · sv , we can add [1] to sy at any time. • The first-order algorithm is similar to the data-weighted averaging algorithm. Oversampling 26-47 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC — Second-Order Example H2(z ) = 1 − z −1 M=4 sv(k ) = VQ[sy(k )] k 0 1 2 3 4 5 6 Oversampling v (k ) 1 1 1 2 0 4 2 se(k ) = sv(k ) − sy(k ) sy(k ) 1, 1, 1, 1 0, 2, 2, 2 0, 1, 3, 3 0, 1, 2, 4 0, 1, 0, 3 1, 2, 0, 4 2, 3, 0, 5 sv(k ) 1, 0, 0, 0 0, 1, 0, 0 0, 0, 1, 0 0, 0, 1, 1 0, 0, 0, 0 1, 1, 1, 1 0, 1, 0, 1 sx(k ) = −2se(k − 1) + se(k − 2) se(k ) +0, −1, −1, −1 +0, −1, −2, −2 +0, −1, −2, −3 +0, −1, −1, −3 +0, −1, +0, −3 +0, −1, +1, −3 −2, −2, +0, −4 26-48 2 sx(k ) −0, +2, +2, +2 −0, +1, +3, +3 −0, +1, +2, +4 −0, +1, +0, +3 −0, +1, −1, +3 −0, +1, −2, +3 +4, +3, +1, +5 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC — Second-Order Example • The element selection logic (ESL) is stable, i.e, se is bounded, for H2(z ) = 1 − z as long as v stays away from the extremes of its range. −1 2 , • When a binary modulator is unstable with an NT F (z ) equal to H2(z ), the corresponding ESL algorithm must also be unstable. • Adding dither to sy may be necessary to whiten the noise caused by a deterministic selection algorithm. Oversampling 26-49 Analog ICs; Jieh-Tsorng Wu Multi-Bit Unit Elements • If polarity reversal or repeated use of an unit element in one period is allowed, the components of sv need not be restricted to {0, 1}. • Multi-bit can enhance the stability of the ESL in the same manner that multi-bit feedback enhances the stability of a regular ∆Σ modulator. • The key circuit constraint is the need to ensure that each usage of an element results in the same error. Oversampling 26-50 Analog ICs; Jieh-Tsorng Wu Decimation and Interpolation Decimation w(n) x(n) h(n) fs Xe f s /M fs π 2π 0 π 2π 2M π π 2π 2π /L 2π ω jω ω 0 π/L 0 π/L Y ej ω 2π Lfs jω 0 We π/M Lfs ω jω y(m) h(n) L Xe Y ej ω Oversampling x(n) jω 0 Interpolation w(m) M fs 0 We y(m) ω 26-51 2π ω ω Analog ICs; Jieh-Tsorng Wu Decimation and Interpolation ∞ Decimation Filter = y (m) = h(k )x (Mm − k ) k =−∞ ∞ Interpolation Filter = y (m) = h(m − kL)x (k ) k =−∞ • The processes of decimation and interpolation are in effect duals. • A filter defined for one process can often be used for other if the same parameters are used. • An architecture that is efficiently defined for one process can often be transposed for used as an efficient architecture in the dual process. Oversampling 26-52 Analog ICs; Jieh-Tsorng Wu Multi-Stage Rate Conversion x(n) y(m) LPF 64 N 2822.4 kHz 44.1 kHz 1+ δ 1 1− δ 1 kHz 20 22.05 1411.2 δ2 ω x(n) LPF 2822.4 kHz 88.2 kHz π y(m) LPF 32 N1 ωs ωp 0 2 N2 44.1 kHz 44.1 kHz 20 Oversampling 66.15 1411.2 kHz 20 22.05 26-53 Analog ICs; Jieh-Tsorng Wu Multi-Stage Rate Conversion • The order N of an equiripple FIR filter is 2 −10 log10(δ1 δ2) − 13 f (δ1, δ2) − g(δ1, δ2)(∆ω) ≈ N≈ ∆ω 14.6∆ω 2 2 f (δ1, δ2) = (0.005309x1 + 0.07114x1 − 0.4761)x2 − (0.00266x1 + 0.5941x1 + 0.4278) g(δ1, δ2) = 11.012 + 0.51244(x1 − x2) ωs − ωp x1 = log10 δ1 x2 = log10 δ2 ∆ω = 2π • For the single-stage design, δ1 = 0.001, δ2 = 0.00001, then N = 6250. For the two-stage design, δ1 = 0.001/2, δ2 = 0.00001, then N1 = 291 and N2 = 205. • Practical considerations sometimes lead to the conclusion that a two-stage design is best. • For most cases, the choice of 2 : 1 for the last stage is both the theoretically best option as well as the most practical one. Oversampling 26-54 Analog ICs; Jieh-Tsorng Wu sinck Filters 1 x(n) z fs 1 2 z M−1 1 z 1 y(m) M f s /M sinc 1 0 x(n) 2π /M 4π /M 8π /M ω π sinc sinc 1 2 y(m) sinc k fs M f s /M x(n) y(m) fs z 1 z 1 z M z M M f s /M x(n) y(m) fs z Oversampling 1 z 1 M z 26-55 1 z 1 f s /M Analog ICs; Jieh-Tsorng Wu sinck Filters The sinc filter transfer function is 1 H1(z ) = M H1 e jω M −1 z −1 i =0 1 = M 1 sin(ωM/2) sinc(ωM/2) · = = M sin(ω/2) sinc(ω/2) −M 1−z 1 − z −1 sin(x ) sinc(x ) = x k The sinc filter transfer function is 1 H (z ) = [H1(z )]k = Mk −M 1−z 1 − z −1 k 1 1 = · 1 − z −1 Mk k · 1 − z −M k • The integrator-differentiator architecture is inherently stable, when 2’s-complement arithmetic is used due to its wrap-around characteristic. Oversampling 26-56 Analog ICs; Jieh-Tsorng Wu Phase-Locked Loops Jieh-Tsorng Wu ES A July 16, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Phase-Locked Loops (PLLs) Ai Phase Detector Ai = g1 (ωi t + θi ) Loop Filter Ao = g2 (ωot + θo) Vc VFO Ao ωo = ωoo + Kc · Vc • g1 and g2 are periodic functions with 2π period. • When the loop is locked, the frequency of the VCO is exactly equal to the average frequency of the input. • The loop filter is a low-pass filter that suppresses high-...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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