Analog Integrated Circuits (Jieh Tsorng Wu)

Good cmrr and psrr less sensitive to waveform the body

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ep response calculation, let Io = −GmVa . Io = −GmVa = sC2 (Vo − Va) + sCLVo C1(Vi − Va) = CpVa + C2(Va − Vo) C2 C2 1−s· G Vo C1 C1 1 − s · Gm m =− ⇒ ACL = =− (C1 +Cp)C2 +(C1+C2 +Cp)CL Vi C2 1 + s · C2 1 + s · τa C 2 Gm τa = (C1 + Cp)C2 + (C1 + C2 + Cp)CL C2Gm C1 + C2 + Cp CL + [(C1 + Cp) C2] = · C2 Gm Open-Loop Unity-Gain Frequency = ωu,OL = Gm CL CL = CL + [(C1 + Cp) C2] C2 Feedback Factor = f = C1 + C2 + Cp Closed-Loop −3 dB Bandwidth = ωu,CL = ωu,OL · f = Opamps-BC 16-13 1 τa Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Step Response The closed-loop step response is Vo(t ) = Vstep 1 − e d Vo dt −t/τa = t =0 Vstep τa The settling time is tsettl e = τa × ln • For 1 =1− Vo(tsettl e ) Vo(∞) < 0.001, require tsettl e > 6.9 × τa. • Total delay can be estimated by td = tsl ew + tsettl e = Opamps-BC Vstep 16-14 SR + τa × ln 1 Analog ICs; Jieh-Tsorng Wu Analog Switches and Sample-and-Hold Circuits Jieh-Tsorng Wu ES A October 8, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Sample-and-Hold (Track-and-Hold) Circuits Switched-Capacitor S/H φ V i φ Vo S/H V Vo i M1 1 C L φH Vo V V o (k) i φ φL kTs Vo(k ) = (1 + ) × Vi (kTs + ∆t ) + Vos S/H 17-2 Analog ICs; Jieh-Tsorng Wu Sample-and-Hold (Track-and-Hold) Circuits Impairments: • Finite bandwidth in sample mode. • Acquisition time and hold settling time. • Aperture jitter ∆t . • Sampling pedestal (Offset VOS and gain error ). • Droop in hold mode. • Feedthrough. • Thermal Noise. S/H 17-3 Analog ICs; Jieh-Tsorng Wu MOST Switches in Sample Mode φ = φH G C S V C gs i C’ sb g on gd D Vo C’ db C L B W W (VGS − Vt ) = µCox (ϕH − Vi − Vt ) L L 1 1 Cgs = Covs + W LCox Cgd = Covd + W LCox 2 2 1 1 Csb = Csb + W LCJ (VSB ) Cd b = Cd b + W LCJ (VDB ) 2 2 gon = µCox S/H 17-4 Analog ICs; Jieh-Tsorng Wu MOST Switches from Sample to Hold Mode V φ φH i Vo φL C G C ov C CH S Q L C ov D CH Vo = Vi + ∆V = (1 + )Vi + VOS • ∆V is due to switch’s clock feedthrough and charge injection. • ∆V depends on the waveform of φ. • Due to the finite slope of φ, the exact turn-off time of the switch depends on Vi . S/H 17-5 Analog ICs; Jieh-Tsorng Wu Switching Errors in Slow-Gating MOST Switches The body effect of MOSTs can be approximately by Vt = Vt0 + γ VS + 2φf − 2φf ≈ Vt0 + (n − 1)Vs • n is a constant, and 1 < n < 2. For slow gating (slow φ fall time), ∆V is due to the clock feedthrough after the switch is turned off. Cov Cov (Vi + Vt − φL) = − (nVi + Vt0 − φL) = Vi + VOS ∆V = − Cov + CL Cov + CL ⇒ S/H Cov = −n · Cov + CL VOS 17-6 Cov = −(Vt0 − φL) · Cov + CL Analog ICs; Jieh-Tsorng Wu Switching Errors in Fast-Gating MOST Switches For fast gating (fast φ fall time), assuming the channel charge QCH is divided equally between input and output, then Cov 1 1 ∆V = −(φH − φL) + QCH = Vi + VOS Cov + CL 2 Cov + CL QCH = −CCH · [(φH − Vi ) − Vt ] = −CCH · (−nVi + φH − Vt0 ) CCH = Cox · W (L − 2LD ) ⇒ CCH n =+ · 2 Cov + CL • In practice, VOS = −(φH − φL) CCH 1 − (φ − Vt0 ) + CL 2 H Cov + CL Cov Cov and VOS decrease with increasing fall time of φ. • The body effect of Vt can cause nonlinearity. S/H 17-7 Analog ICs; Jieh-Tsorng Wu MOST S/H Speed-Precision Tradeoff W Vov L Charge Injection = ∆Q = α · Q On Conductance = gon = µCox Vi Vi Q V C 2 Q = Cox W LVov L = gon · µ Time Constant in Sampling Mode = τon = 2 αL ∆Q = Absolute Voltage Error = ∆V = µτon C C gon 2 ∆V αL Relative Voltage Error = = Vi µτonVDD • Want Ts,on > 7τon for a 0.1% settling accuracy, where Ts,on is the sampling time. • α can be reduced by compensation. • Relative error ∆V/Vi is increased when reducing VDD . S/H 17-8 Analog ICs; Jieh-Tsorng Wu Aperture Jitter Due to the Finite Falling Time (k-1)Ts kTs φ Vi tf Vo C VDD φ Vi Vt 0 t t kTs VDD − (Vi + Vt ) ∆t = tf × VDD 0 ≤ ∆t ≤ tf 1 − Vt0 VDD • The jitter is input dependent, and introduces noise at output. S/H 17-9 Analog ICs; Jieh-Tsorng Wu Thermal Noise in MOST S/H Ts R on Vi Vo Vi m Ts Vo C C S Sn (f) H Sn (f) During sampling mode, the two-sided noise PSD at Vo is S Sn (f ) = Sn(f ) = 4kT Ron 1 1 · 4kT Ron · |H (j 2πf )|2 = · 2 2 1 + (2πf RonC)2 Bn = 1 4RonC • For sampling rate fs = 1/Ts , want Ts,on = m · Ts > 7 · RonC S/H ⇒ 17-10 Bn > 71 · · fs 4m or Bn ≥ 5fs Analog ICs; Jieh-Tsorng Wu Thermal Noise in MOST S/H During the hold mode, the noise is sampled and the noise PSD is ∞ H Sn (f ) = i =−∞ 1/(2Ron C) 2Bn kT 1 · Sn(f − i · fs ) ≈ × Sn(f ) ≈ × 2kT Ron = fs fs C fs • It is assumed that Bn fs . • The total noise power in the baseband −fs /2 ≤ f ≤ fs /2 is hence kT /C. • Want large C for low-noise performance. • Reference: Roubik Gregorian and Gabor Temes, “Analog MOS Integrated Circuits for Signal Processing,” John Wiley & Sons, Inc., 1986. S/H 17-11 Analog ICs; Jieh-Tsorng Wu Charge Compensation for MOST Switches φ Vo M1 V φ φ V i R S C M2 i R ∆Q2 ∆Q1 Vo M1 M2 φ C L Dummy Switch ∆Q2...
View Full Document

Ask a homework question - tutors are online