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Unformatted text preview: Wu D/A Performance Metrics — Static Characteristics
• Resolution: number of bits (N), analog 1 LSB step (∆).
• Oﬀset error.
• Gain error.
• Integral nonlinearity (INL).
• Diﬀerential nonlinearity (DNL).
• Monotonicity.
– Monotonicity can be assumed if the DNL > −1 LSB.
• Stability.
– Variation with time, temperature, and supply voltage.
DACs 2410 Analog ICs; JiehTsorng Wu D/A Performance Metrics — Dynamic Characteristics
• Sampling rate.
• Settling time.
– Settling time is the time taken by the D/A output to settle within some speciﬁed
error band (typically ± 1 LSB).
2
– The settling time is primarily dominated by the settling of the MSB contribution.
• Glitch impulse area (glitch energy).
– Glitches is the output transient spikes during the conversion process.
– Glitches are caused by the unequal delays in switching various signal sources
within the converter.
• Dynamic range: SNRmax , SFDR, SINAD. DACs 2411 Analog ICs; JiehTsorng Wu Dynamic Range x(k) Quantizer
NBit y(k) NBit
DAC y(t) Power Spectrum
dBm/Hz
y(t)
SFDR fs
e(k)
fi
x(k) y(k) SINAD
(dB) 2fi f 3fi Ideal Probability Density Function (pdf) Measured e
/2 DACs dB /2 0
Input Level Relative to Full Scale 2412 Analog ICs; JiehTsorng Wu Dynamic Range
e(k ) is a quantization noise due to the quantization process.
e(k ) ≡ y (k ) − x (k ) Noise Power = Pn = 12
∆
e pdf(e)d e =
12
2 Let the input x (k ) be a sinusoidal waveform
1
Signal Power = Ps = A2
2 x (k ) = A sin(2πfi · kTs )
The signaltonoise ratio of y (k ) is
Ps 2 A
=6·
SNR ≡
Pn
∆2
When the input’s amplitude A = AF S /2, the SNR reaches its maximum value.
AF S = 2N ∆ DACs Ps = 1 2N 2
·2 ∆
8 SNRmax = 22N × 2413 3
= N × 6.02 dB + 1.76 dB
2
Analog ICs; JiehTsorng Wu Dynamic Range
• The ratio between fs and fi should be irrational.
• In the discretetime domain, noise power of e(k ) is assumed to be uniformly
2
distributed between −Ωs /2 and +Ωs /2. The power density is ∆ /(12Ωs ).
• The spurious free dynamic range (SFDR) is the ratio of the fundamental signal
component to the largest distortion component when A = AF S /2.
• The signaltonoise plus distortion ratio (SINAD) is the ratio of power of the
fundamental signal to the total power of noise and distortion when A = AF S /2.
• The total harmonic distortion (THD) is the ratio of the total power of the 2nd and higher
harmonic components to the power of the fundamental signal.
• In ﬁnding the total noise power, the noise bandwidth need to be speciﬁed. DACs 2414 Analog ICs; JiehTsorng Wu ResistorString DACs with Digital Decoding
Din Vref N • Inherently monotonic. R Decoder • DNL depend on local matching of neighboring R’s. 1 of 2 N R R • INL depends on global matching of the Rstring.
• No resistive load at Vo.
• The worstcase time constant occurs a the
midpoint of the Rstring.
• Large capacitive loading at Vo. Vo
DACs 2415 Analog ICs; JiehTsorng Wu Folded RString DACs with Digital Decoding 1 of 2 M Decoder Vref (MSBs) M Vo
1 of 2 DACs NM Decoder 2416 NM N Din Analog ICs; JiehTsorng Wu RString DACs with BinaryTree Decoding
Vref b 0 b 0 b 1 b 1 b 2 b 2 R R R • Require no digital decoder.
R R Vo • Speed is limited by the delay through
the resistor string as well as the
delay through the switch network. R R R DACs 2417 Analog ICs; JiehTsorng Wu Intermeshed ResistorString DACs (OneLevel Multiplexing)
Vref Vo DACs 2418 Analog ICs; JiehTsorng Wu Intermeshed ResistorString DACs (TwoLevel Multiplexing)
Vref Vo DACs 2419 Analog ICs; JiehTsorng Wu BinaryWeighted CurrentSteering DACs
Io VB VB 2 N1 VB N2 I 2
b N1 I 2 0 b N2 I
b0 Io = I · bN −1 · 2N −1 + bN −2 · 2N −2 + · · · + b1 · 21 + b0 · 20 DACs 2420 Analog ICs; JiehTsorng Wu BinaryWeighted CurrentSteering DACs
• Fast.
• Monotonicity is not guaranteed.
• Potentially large glitches due to timing skews.
• Latches are often used to synchronize bN −1, bN −2, . . . .
• Ro of the current sources can cause nonlinearity. Io Glitch t
D in = 0111
DACs D in = 1000
2421 Analog ICs; JiehTsorng Wu BinaryWeighted R2R Networks
16 I
8I 4I 2R 2I 2R 1I 2R 1I 2R 16 I
R R R 2R 8I 2R 2I I I x8 VB 4I x4 x2 x1 x1 R 2R R 2R R 2R 2R VEE • No widerange scaling of resistors.
• BJT emitterarea scaling can be conﬁned to the ﬁrst few MSBs; and the voltage drops
in the emitter resistors should dominate the VBE (on) mismatches of the less signiﬁcant
bits.
DACs 2422 Analog ICs; JiehTsorng Wu EquallyWeighted CurrentSteering DACs
Io
VB VB I I
1 Din VB I
2N 1 2 N
Binary toThermometer Decoder • Inherently monotonic.
• Glitches are reduced. Synchronizing latches may be still required. DACs 2423 Analog ICs; JiehTsorng Wu The Matrix Floorplan
Din N LSBs MSBs M Column Decoder
Cj Row Decoder Cj Ri Io Local
Decoder Ri • Rj is a 2M − 1 thermometer code, and Cj is a 2N −M − 1 thermometer code.
• One example of the local decoding is S = Ri +1 + Ri · Cj .
• INL may exhibit the gradient of the unit cell’s variations.
• INL can be dithered by jump...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.
 Winter '09
 Choma
 Integrated Circuit, Transistor, The Land

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