Analog Integrated Circuits (Jieh Tsorng Wu)

Hybrid dac 1 l 2c l dac 2 2c l 1 2 c bj vo 1 2c 0 2c

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Unformatted text preview: Wu D/A Performance Metrics — Static Characteristics • Resolution: number of bits (N), analog 1 LSB step (∆). • Offset error. • Gain error. • Integral nonlinearity (INL). • Differential nonlinearity (DNL). • Monotonicity. – Monotonicity can be assumed if the DNL > −1 LSB. • Stability. – Variation with time, temperature, and supply voltage. DACs 24-10 Analog ICs; Jieh-Tsorng Wu D/A Performance Metrics — Dynamic Characteristics • Sampling rate. • Settling time. – Settling time is the time taken by the D/A output to settle within some specified error band (typically ± 1 LSB). 2 – The settling time is primarily dominated by the settling of the MSB contribution. • Glitch impulse area (glitch energy). – Glitches is the output transient spikes during the conversion process. – Glitches are caused by the unequal delays in switching various signal sources within the converter. • Dynamic range: SNRmax , SFDR, SINAD. DACs 24-11 Analog ICs; Jieh-Tsorng Wu Dynamic Range x(k) Quantizer N-Bit y(k) N-Bit DAC y(t) Power Spectrum dBm/Hz y(t) SFDR fs e(k) fi x(k) y(k) SINAD (dB) 2fi f 3fi Ideal Probability Density Function (pdf) Measured e /2 DACs dB /2 0 Input Level Relative to Full Scale 24-12 Analog ICs; Jieh-Tsorng Wu Dynamic Range e(k ) is a quantization noise due to the quantization process. e(k ) ≡ y (k ) − x (k ) Noise Power = Pn = 12 ∆ e pdf(e)d e = 12 2 Let the input x (k ) be a sinusoidal waveform 1 Signal Power = Ps = A2 2 x (k ) = A sin(2πfi · kTs ) The signal-to-noise ratio of y (k ) is Ps 2 A =6· SNR ≡ Pn ∆2 When the input’s amplitude A = AF S /2, the SNR reaches its maximum value. AF S = 2N ∆ DACs Ps = 1 2N 2 ·2 ∆ 8 SNRmax = 22N × 24-13 3 = N × 6.02 dB + 1.76 dB 2 Analog ICs; Jieh-Tsorng Wu Dynamic Range • The ratio between fs and fi should be irrational. • In the discrete-time domain, noise power of e(k ) is assumed to be uniformly 2 distributed between −Ωs /2 and +Ωs /2. The power density is ∆ /(12Ωs ). • The spurious free dynamic range (SFDR) is the ratio of the fundamental signal component to the largest distortion component when A = AF S /2. • The signal-to-noise plus distortion ratio (SINAD) is the ratio of power of the fundamental signal to the total power of noise and distortion when A = AF S /2. • The total harmonic distortion (THD) is the ratio of the total power of the 2nd and higher harmonic components to the power of the fundamental signal. • In finding the total noise power, the noise bandwidth need to be specified. DACs 24-14 Analog ICs; Jieh-Tsorng Wu Resistor-String DACs with Digital Decoding Din Vref N • Inherently monotonic. R Decoder • DNL depend on local matching of neighboring R’s. 1 of 2 N R R • INL depends on global matching of the R-string. • No resistive load at Vo. • The worst-case time constant occurs a the midpoint of the R-string. • Large capacitive loading at Vo. Vo DACs 24-15 Analog ICs; Jieh-Tsorng Wu Folded R-String DACs with Digital Decoding 1 of 2 M Decoder Vref (MSBs) M Vo 1 of 2 DACs N-M Decoder 24-16 N-M N Din Analog ICs; Jieh-Tsorng Wu R-String DACs with Binary-Tree Decoding Vref b 0 b 0 b 1 b 1 b 2 b 2 R R R • Require no digital decoder. R R Vo • Speed is limited by the delay through the resistor string as well as the delay through the switch network. R R R DACs 24-17 Analog ICs; Jieh-Tsorng Wu Intermeshed Resistor-String DACs (One-Level Multiplexing) Vref Vo DACs 24-18 Analog ICs; Jieh-Tsorng Wu Intermeshed Resistor-String DACs (Two-Level Multiplexing) Vref Vo DACs 24-19 Analog ICs; Jieh-Tsorng Wu Binary-Weighted Current-Steering DACs Io VB VB 2 N-1 VB N-2 I 2 b N-1 I 2 0 b N-2 I b0 Io = I · bN −1 · 2N −1 + bN −2 · 2N −2 + · · · + b1 · 21 + b0 · 20 DACs 24-20 Analog ICs; Jieh-Tsorng Wu Binary-Weighted Current-Steering DACs • Fast. • Monotonicity is not guaranteed. • Potentially large glitches due to timing skews. • Latches are often used to synchronize bN −1, bN −2, . . . . • Ro of the current sources can cause nonlinearity. Io Glitch t D in = 0111 DACs D in = 1000 24-21 Analog ICs; Jieh-Tsorng Wu Binary-Weighted R-2R Networks 16 I 8I 4I 2R 2I 2R 1I 2R 1I 2R 16 I R R R 2R 8I 2R 2I I I x8 VB 4I x4 x2 x1 x1 R 2R R 2R R 2R 2R VEE • No wide-range scaling of resistors. • BJT emitter-area scaling can be confined to the first few MSBs; and the voltage drops in the emitter resistors should dominate the VBE (on) mismatches of the less significant bits. DACs 24-22 Analog ICs; Jieh-Tsorng Wu Equally-Weighted Current-Steering DACs Io VB VB I I 1 Din VB I 2N -1 2 N Binary- to-Thermometer Decoder • Inherently monotonic. • Glitches are reduced. Synchronizing latches may be still required. DACs 24-23 Analog ICs; Jieh-Tsorng Wu The Matrix Floorplan Din N LSBs MSBs M Column Decoder Cj Row Decoder Cj Ri Io Local Decoder Ri • Rj is a 2M − 1 thermometer code, and Cj is a 2N −M − 1 thermometer code. • One example of the local decoding is S = Ri +1 + Ri · Cj . • INL may exhibit the gradient of the unit cell’s variations. • INL can be dithered by jump...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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