Unformatted text preview: 1,D2 > ID3,D4, i.e., I1 > ID9,D10,
• Without M11 and M12, the slew rate is
SR = ID9
CL = ID10
CL • During slew condition, M11 and M12 can be used to clamp the drain volage of M1
and M2 to reduce bias recovery time, and increase ID9 and ID10 to improve SR.
If bias currents ID1,D2 < ID3,D4, i.e., I1 < ID9,D10,
• This slew rate is
SR = I1
CL I1 = ID1 + ID2 • M11 and M12 are not required.
OpampII 148 Analog ICs; JiehTsorng Wu CurrentMirror Operational Ampliﬁer
VDD M3 M4 M6 M5
V ccp M9
M10
V
V M12 M11
Vo i+ M1 M2
V ccn M13
M14 iI M7 1 M8 C L VSS OpampII 149 Analog ICs; JiehTsorng Wu CurrentMirror Operational Ampliﬁer
W
L =
3 W
L =
4 W
L 6 ID1,D2 = ID3,D4 = ID6 = ID7
Av (0) = K gm1Ro Ro = 1
=
K W
L 1
1
1
= ID5 = ID8 = I1
2
K
K
1 g o5
gm11 ro11 5 W
L +g g o8
m14 ro14 p1 = − 7 1
=
K W
L 8 K I1
SR =
CL
1
RoCL ωu = K gm1
CL • For a given power dissipation, the currentmirror opamps have larger bandwidth and
SR than the foldedcascode opamps. But they also suﬀer from larger thermal noise.
• For small CL, K may have to be reduced to prevent the nondominant poles from
degrading the phase margin.
• A practical upper limit on K is around 5. For a generalpurpose opamp, K OpampII 1410 2. Analog ICs; JiehTsorng Wu RailtoRail Complementary Input Stage
VDD
I 1p I 2p
V i+ V i Io,n1 Ip
M3 Io,n2 M4 V i+ V iM1 V i+ V i M2
Io,p2 In I 2n I 1n Io,p1 VSS
OpampII 1411 Analog ICs; JiehTsorng Wu RailtoRail Complementary Input Stage
• Total input stage transconductance is
Gm = gm1 + gm3
• Gm variation due to Vi c change can degrade CMRR. Want
gm1 + gm3 = µnCox (W/L)1 In + µpCox (W/L)3 Ip = Constant If µn Cox (W/L)1 = µpCox (W/L)3 , want
In + OpampII Ip = I1n − I2p + 1412 I1p − I2n = Constant Analog ICs; JiehTsorng Wu RailtoRail Complementary Input Stage
• Let
At Vi c I1n = I1p = 4I
(VDD − VSS )/2
In + At Vi c Ip = 1I + 1I = 2 I Ip = 0I + 4I = 2 I Ip = 4I + 0I = 2 I VSS , In = 0 and I2n = 0,
In + At Vi c I2n = I2p = 3I VDD , Ip = 0 and I2p = 0,
In + • Less than 5% change in Gm is possible.
• The variation of the inputreferred dc oﬀset VOS due to Vi c change also degrade
CMRR.
OpampII 1413 Analog ICs; JiehTsorng Wu A RailtoRail Input/Output Opamp
VDD
Ip M11 M12 Cc V ccp M13
M14
M3 M4 V i+ V iM1 M21 M2 V bop
M23 M25
M24 Vo V bon
M26 V ccn M17 M22 C L M18
I n M15 M16 Cc VSS OpampII 1414 Analog ICs; JiehTsorng Wu A RailtoRail Input/Output Opamp
• Two cascaded gain stages.
• Noises in Vbop and Vbon are canceled at output.
• The bias of the output stage is insensitive to variations in Ip, In and supply voltage.
• The two Cc are connected as Miller frequency compensation using commongate
stages.
• The output pole is
p2 = Cc
gmo
×
Cgso
CL where gmo and Cgso are respectively the total gm and Cgs of the output stage.
• Reference: Hogervorst, et al., JSSC 12/94, pp. 1505–1513. OpampII 1415 Analog ICs; JiehTsorng Wu LowVoltage MultiStage Opamp
VDD M5 M6 M7
M8 M1 V i+ C2a M2 V C2b M9
M10 i M11
C3 C1a
Vo Bias
M3
M4 C1b
M12 VSS OpampII 1416 Analog ICs; JiehTsorng Wu LowVoltage MultiStage Opamp
• Four cascaded gain stages.
• Hybrid nested Miller compensation.
• ClassAB output stage.
• A supply voltage below 1.5 V is possible.
• Reference: Eschauzier, et al., JSSC 12/94, pp. 1497–1504. OpampII 1417 Analog ICs; JiehTsorng Wu CurrentFeedback Conﬁguration
R2 R2 R1 R1 Vi
Vx Io Vi
Vo Vo
Ix RL Zi RL CurrentFeedback Opamp VoltageFeedback Opamp For the voltagefeedback opamp, let Vo/Vx = A ≈ ωu/s and Zi → ∞, then
Vo
R2
1
=− ·
Av =
Vi
R1 1 + 1 1 + R2
A
R
1 R2
1
≈− ·
R1 1 + s 1 + R2
ω
R
u 1 • Tradeoﬀ between closedloop gain and closedloop bandwidth.
OpampII 1418 Analog ICs; JiehTsorng Wu CurrentFeedback Conﬁguration
For the currentfeedback opamp, let Io/Ix = A ≈ ωu/s, then
Vo Z 1 − ARi R2
R2
2
Av =
≈− ·
=− ·
R1 R2+Zi (R1 +R2+RL )
Vi
R1 1 + 1 1 +
R1
A
RR
1L 1
s
1+ ω u If Zi → 0,
Av ≈ − R2
1
·
R1 1 + s
ω
u 1+ R +R
R2 +Zi 1+ 2R L
1 RL R2
RL • The closedloop gain can be modiﬁed by changing R1, leaving the closedloop
bandwidth unchanged.
• For a given R2, frequency compensation can be optimized.
frequency applications.
OpampII 1419 Suitable for high Analog ICs; JiehTsorng Wu A CMOS CurrentFeedback Driver
VDD 2I I
Vo V ccp M11 M21 M1
R2 M3
M23
V
icm Vi
R1 Vo V bop
V bon M24 M4
M2
V ccn M12 M22 R L 2I I VSS OpampII 1420 Analog ICs; JiehTsorng Wu A CMOS CurrentFeedback Driver
• This opamp has been designed to drive RL = 25 Ω and provide 50 mA of output
current.
• Twostage opamp with only one highimpedance node.
• Cgs and Cgd of M21 and M22 are large enough to provide adequate frequency
compensation.
• The classAB commongate input stage provides large internal slew rate.
• Large voltage swing of Vgs21 and Vgs22 are required.
• Openloop current gain is determined by the output stage,
A(s) ≈ gmo
sCgo ωu
=
s ωu = gmo
Cgo • Loop gain T (s) ≈ A(s)RL /(RL + R2) is independent...
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 Winter '09
 Choma
 Integrated Circuit, Transistor, The Land, Bipolar junction transistor, VDS, Analog ICs, JiehTsorng Wu

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