Analog Integrated Circuits (Jieh Tsorng Wu)

If p1 p2 p3 1 p1 cc2 1 p2 cc1 p3 the two pole

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Unformatted text preview: C1 R2 p 2 p 1 p’ 1 C2 Let f = 0, the nodal equations are G1 + s(C1 + Cc) gm2 − sCc Feedback −sCc G2 + s(C2 + Cc) 12-31 −gm1vi v1 = v2 0 Analog ICs; Jieh-Tsorng Wu Miller (Pole-Splitting) Compensation The open-loop forward gain a(s) can be solved as 1 − s/z1 1 − s/z1 v2 = a0 × = a0 × a (s ) ≡ 2 vi D (s) 1 + b1s + b2s a0 = gm1gm2R1R2 gm2 z1 = + Cc b1 = R1(C1 + Cc) + R2(C2 + Cc) + gm2R1R2Cc Using dominant-pole approximation, i.e., |p1| b2 = R1R2(C1C2 + C1Cc + C2Cc) |p2|, 1 1 p1 ≈ − = − b1 R1 (C1 + Cc) + R2(C2 + Cc) + gm2R1R2Cc R1 (C1 + Cc) + R2(C2 + Cc) + gm2R1R2Cc b1 p2 ≈ − = − b2 R1R2 (C1C2 + C1Cc + C2Cc) Feedback 12-32 Analog ICs; Jieh-Tsorng Wu Miller (Pole-Splitting) Compensation Further, if gm2R2 1, R1 ∼ R2 , and C1 ∼ C2 ∼ Cc, then gm1 1 1 p1 ≈ − =− × a0 gm2R1R2Cc Cc p2 ≈ − gm2Cc gm2 ≈− C1C2 + C1Cc + C2Cc C1 + C2 The dominant-pole unity-gain frequency is gm1 ωu = |ao| × |p1 | = Cc • Note that if Cc = 0 p1 = − 1 R1 C1 p2 = − 1 R2C2 • Cc acts as a pole splitting capacitor that separate p1 and p2 . Feedback 12-33 Analog ICs; Jieh-Tsorng Wu Miller (Pole-Splitting) Compensation For a given phase margin, we have f · ωu = αp · |p2 | Thus ω−3dB ≈ ωt = αt · |p2 | |p2| Cc gm2 f = = × αp gm1 C1 + C2 ωu And Cc can be determined by gm1 f × × (C1 + C2) Cc = αp gm2 • For compensation of a general-purpose opamp, let f = 1, then ωu = αp · |p2 | Feedback gm1 1 Cc = × × (C1 + C2) αp gm2 12-34 Analog ICs; Jieh-Tsorng Wu Feedforward Zero in Miller Compensation • Because z1 is in the right half-plane (RHP), it will degrade the amplifier phase margin as it approaches f · ωu. dB |a| • z1 is caused by the feedforward path of Cc. log ω p’ 1 z’ 1 ic = sCc(v2 − v1) = sCc v2 − sCc v1 p’ 2 Deg ∠a • To avoid degrading of phase margin by z1, log ω want z1 90 180 Feedback f · ωu ⇒ z1 gm2 ≈ ωu gm1 f • Otherwise, additional circuitry must be added to move z1. 12-35 Analog ICs; Jieh-Tsorng Wu Miller Compensation With Unity-Gain Buffer VDD Cc Mc Assume the voltage gain of the Mc source follower is 1. Then ic Fbk Vi VSS gm1 R1 a(s) = Feedback v1 gm2 C1 R2 v2 Vo ic = sCc(v2 − v1) −gm2v1 = v2(G2 + sC2 ) C2 gm1gm2R1R2 1 + s[R1 (C1 + Cc) + R2C2 + gm2R2R1Cc] + s2 R1R2C2(C1 + Cc) gm2 1 p2 ≈ − p1 ≈ − gm2R1R2 Cc C1 + C2 12-36 Analog ICs; Jieh-Tsorng Wu Miller Compensation With Common-Gate Stage VDD Cc VB Fbk Vi gm1 v1 Assume the input impedance of the Mc common-gate stage is 0. Then Mc ic v2 gm2 Vo ic = sCc · v2 −gm2v1 = v2(G2 + sC2 + sCc) R1 a(s) = C1 R2 C2 gm1gm2R1R2 1 + s[R1 C1 + R2(C2 + Cc) + gm2R2R1Cc] + s2 R1R2C1(C2 + Cc) 1 p1 ≈ − gm2R1R2Cc Feedback Cc gm2 p2 ≈ − · C2 + Cc C1 12-37 Analog ICs; Jieh-Tsorng Wu Miller Compensation With Nulling Resistor Cc RZ Fbk Vi gm1 v1 R1 gm2 C1 a(s) = gm1gm2R1R2 · v2 R2 Vo C2 1 − sCc 1/gm2 − RZ 1 + b1s + b2s2 + b3s3 b1 = R2 (C2 + Cc) + R1(C1 + Cc) + RZ Cc + gm2R1R2Cc b2 = R1 R2(C1C2 + CcC1 + CcC2) + RZ Cc(R1 C1 + R2C2) b3 = R1 R2RZ C1C2Cc Feedback 12-38 Analog ICs; Jieh-Tsorng Wu Miller Compensation With Nulling Resistor We have z1 = 1 p1 ≈ − gm2R2R1 Cc • In most cases, p3 1 (1/gm2 − RZ )Cc gm2 p2 ≈ − C1 + C2 1 p3 ≈ − RZ C1 p1,2. • Usually want z1 becomes negative and 1 = 1.2ωu |z1| ≈ RZ Cc Feedback ⇒ gm1 1 = 1.2 · RZ Cc Cc 12-39 ⇒ RZ = 1 1.2gm1 Analog ICs; Jieh-Tsorng Wu Miller Compensation with Feedforward Transconductor Cc Fbk Vi v1 gm1 R1 v2 gm2 C1 R2 Vo C2 gmf a(s) = gm1R1gm2R2 + gmf R2 + sR1 R2[gmf (C1 + Cc) − gm1Cc] 1 + s[R1 (C1 + Cc) + R2(C2 + Cc) + gm2R1R2Cc] + s2 [R1R2 (C1C2 + C1Cc + C2Cc)] To remove zero, let Feedback gmf = gm1 · 12-40 Cc C1 + Cc = gm1 · 1 1 + C1/Cc Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation C c2 C c1 Fbk Vi v1 gm1 R1 gm2 C1 v2 R2 gm3 C2 R3 v3 Vo C3 2 a0 + a1 s + a2 s N (s) a(s) = = D (s) 1 + b1s + b2s2 + b3s3 a0 = gm1gm2gm3R1R2R3 a1 = −(gm2 R2Cc1 + Cc2)gm1 R1R3 a2 = −gm1R1R2 R3Cc2(C2 + Cc1 ) Feedback 12-41 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation b1 = K + R1(Cc2 + C1) + gm2R2gm3R3R1 Cc2 2 b2 = R2 R3(C3 + Cc1 + Cc2 )(C2 + Cc1 ) − R2R3Cc1 + R1(Cc2 + C1)K 2 − gm2R2Cc1Cc2 R1R3 − R1R3Cc2 b3 = R1 R2R3[(C3 Cc2 + C1C3 + C1Cc2)(C2 + Cc1 ) + C1Cc1Cc2 + C1 C2Cc1] K = R3 (C3 + Cc1 + Cc2) + R2(C2 + Cc1 ) + R2Cc1gm3R3 The dominant pole is 1 p1 ≈ − R1Cc2 (gm2R2gm3R3) If Cc1 C1,2, then |p2| p2 ≈ − Feedback |p3 |, and gm2gm3 (gm3 − gm2)Cc1 p3 ≈ − (gm3 − gm2)Cc1 C2C3 + Cc1(C2 + C3) 12-42 ≈− gm3 − gm2 C2 + C3 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation • To ensure p2 and p3 are in the LHP, want gm3 > gm2. • If |p1 | |p2| |p3|, 1 p1 ∝ Cc2 1 p2 ∝ Cc1 p3 ≈ − The two-pole model can be used by making |p3 | gm3 − gm2 C2 + C3 ωt . • If Cc1 is not large enough, p2 and p3 are either complex conjugates or real but closely spaced. Higher unity-gain bandwidth may be achievable when p2 and p3 are not real and widely separated. Feedback 12-43 Analog ICs; Jieh-Tsorng Wu Zeros in the Nested-Miller Compensation The numerator of a(s) is N (s) = gm1R1gm2R2gm3 Assuming Cc1 C2 and Cc1 Cc2 C (C2 + Cc1) Cc1 2 c2 1−s −s + gm3 gm2R2gm3 gm2gm3 Cc2/(gm2 R2), then N (s) ≈ gm1R1gm2R2gm3 gm2 1 + z1 = − 2Cc2 1+ 4gm3Cc2 gm2Cc1 Cc1 CC 2 c2 c1 1−s −s gm3 gm2gm3 4g C gm2 1 − 1 + m3 c2 z2 = − 2Cc2 gm2Cc1 • z1 is a LHP zero and z2 is a RHP zero. |z1| > |z2| • |z1| and/or |z2| can be comparable to |p2|, thus degrading phase margin. Feedback 12-4...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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