Analog Integrated Circuits (Jieh Tsorng Wu)

Large geometry structures can achieve a vt with

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Unformatted text preview: Since VOS = VID = VBE 1 − VBE 2 , we have VOS = UT ln Differential Gain Stages IC1 IS 1 − UT ln IC2 IS 2 = UT ln IC1 IS 2 IC2 IS 1 7-17 RC2 A2 G1(VCB1 ) = UT ln · · RC1 A1 G2(VCB2 ) Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Offset Voltage To describe the mismatch in the components, using X1 + X2 X= 2 ∆X = X1 − X2 ⇒ X1 = X + ∆X 2 X2 = X − ∆X 2 Then VOS = UT ln RC − RC + ∆RC 2 ∆RC 2 Differential Gain Stages 1 ∆RC 2 RC 2 RC ∆RC RC 1− 1 − 1 ∆A 1 + 1 ∆G A − ∆A G + ∆G 2G 2A 2 2 · · · = UT ln · · ∆A ∆G 1 ∆A 1 ∆G ∆RC A+ 2 G− 2 1+ 2 A 1− 2 G 1+1 1, ln(1 + y ) = y − From Taylor series, if y VOS ≈ UT − ∆A ∆G + − A G y2 2 + or 7-18 y3 3 − · · · ≈ y . We have VOS = UT − ∆RC RC − ∆IS IS Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Offset Voltage • The offset voltage drift due to temperature variation is d VOS d = dT dT kT q − ∆RC RC − ∆IS IS ∆RC ∆IS k = − − q RC IS = VOS T • Nulling VOS usually doesn’t null d VOS /d T because of how it is accomplished. ◦ • VOS drifts in the 1 µV/ C range can be obtained with careful design. Rx Rx VCC VCC R C2 R C2 R C1 R C1 Q1 Differential Gain Stages Q2 Q1 7-19 Q2 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Offset Current The input offset current is defined as IOS ≡ IBD |VOD =0 = IB1 − IB2 = IC1 βF 1 − IC2 βF 2 As before, the formula can be arranged as IOS = IC + βF + ∆IC 2 ∆βF 2 − IC − βF − ∆IC 2 ∆βF 2 ≈ IC ∆IC βF IC − ∆βF βF Since VOD = 0, we have IC1RC1 = IC2RC2 ⇒ ∆IC IC =− ∆RC RC ⇒ IOS ≈ − IC ∆RC βF RC ∆βF + βF • A typical βF mismatch distribution displays a deviation of about 10%. Differential Gain Stages 7-20 Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair Input Offset Voltage VDD VDD R D1 R D2 RD Vo M1 V Vo OS M2 Vi RD M1 M2 Vi I SS I SS VSS VSS Circuit with No Mismatches VOS = VGS 1 − VGS 2 Differential Gain Stages VGS = Vt + 7-21 2ID k (W/L) k = µCox Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair Input Offset Voltage Since VOD = 0, we have ID1RD1 = ID2RD2 ∆ID ∆RD =− ID RD ⇒ The offset voltage is VOS = VGS 1 − VGS 2 = ∆Vt + 2ID k (W/L) × 1+ 1+ 1 2 1 ∆ID 2 ID ∆(W/L) (W/L) − 1− 1− 1 2 1 ∆ID 2 ID ∆(W/L) (W/L) Using Taylor series, VOS VGS − Vt ∆ID ∆(W/L) VGS − Vt ∆RD ∆(W/L) − ≈ ∆Vt + − − ≈ ∆Vt + 2 2 ID RD (W/L) (W/L) VGS − Vt ≡ Differential Gain Stages 2ID k (W/L) = Vov = 2[(ID1 + ID2)/2] 7-22 k (W/L) = ISS k (W/L) Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair Input Offset Voltage • ∆Vt can be minimized by careful layout. Large-geometry structures can achieve a ∆Vt with standard deviations on the order of 2 mV in modern MOS process. • Due to the VGS − Vt term, offset in MOST pairs is typically 10 times larger than that of BJT pairs. • Both Vt and Vov have a strong temperature dependence, affecting VGS in opposite directions. • d VOS /d T in MOST pairs is not well correlated with VOS , unlike BJT pairs. Differential Gain Stages 7-23 Analog ICs; Jieh-Tsorng Wu Unbalanced Resistor Circuit Analysis id i1 R1 2 i2 v1 R2 ic v2 ic vd ∆R 2 2 vc R Differential HC id vd = v1 − v2 = i1R1 − i2R2 = ic + 2 v1 + v2 = vc = 2 Differential Gain Stages ic + id 2 ∆R R+ 2 id − ic − 2 R + ∆R + ic − 2 2 7-24 id 2 R − ∆R 2 id ∆R 22 R Common-Mode HC ∆R R− 2 = id R + ic(∆R ) ∆R = icR + id 4 Analog ICs; Jieh-Tsorng Wu Unbalanced gm Circuit Analysis id ic 2 i1 i2 gm1 v1 gm2 v2 v gm d 2 ∆gm vc 2 Differential HC ∆gm id = i1 − i2 = gm + 2 i1 + i2 = ic = 2 Differential Gain Stages gm + ∆gm 2 vd vc + 2 vc + vd 2 ∆gm − gm − 2 − gm − 2 7-25 ∆gm 2 gm vc Common-Mode HC vd vc − 2 vc − ∆gm vd 22 vd 2 = gmvd + ∆gmvc ∆gmvd = g m vc + 4 Analog ICs; Jieh-Tsorng Wu Unbalanced Differential Amplifier R1 vo1 R2 ∆R ic 2 R id ∆R 22 id 2 vod 2 vo1 vic gm v1 vs gm2 vi2 v gm id 2 RSS ic voc v1 gm1 vi1 R ∆gm v1 2 2RSS ∆gm vid 22 Common-Mode HC Differential HC If ∆R = 0 and ∆gm = 0, we have Ad m = −gmR Differential Gain Stages Acm gm R =− 1 + 2gmRSS 7-26 Acd m = 0 Ad cm = 0 Analog ICs; Jieh-Tsorng Wu Unbalanced Differential Amplifier Including mismatches, the voltage gains are vod Ad m = voc Ad cm Acd m Acm vi d vi c where Ad m vod = vi d Acd m Ad cm voc = vi d vi c =0 vod = vi c voc vi c ∆gm R 2 − ∆gm ∆R 22 1 + 2gmRSS gm∆R + ∆gmR =− 1 + 2gmRSS vi d =0 1 = − gm∆R + 4 vi d =0 Acm = Differential Gain Stages = −gmR + ∆gmRSS ∆gmR − gm∆R 2gmRSS 1 + 2gmRSS =− vi d =0 7-27 gm R + ∆ gm 2gm 2 ∆gm ∆R 22 1 + 2gmRSS Analog ICs; Jieh-Tsorng Wu Simplified Analysis for Unbalanced Differential Amplifier ˆ ˆ ˆ First assume no mismatches, and find Ad m, Acm, vod , iˆd , voc, iˆc, and v1, Ad m = −gmR Acm gm R =− 1 + 2gmRSS ˆ vod = Ad mvi d = −gmRvi d gmRvi c vi c ˆ ˆ voc = Acvi c = − v1 = 1 + 2gmRSS 1 + 2gmRSS Then consider only the mismatch terms, v ∆g ˆc ∆R − R m v1 = od ˆ −i 2 2 2 ⇒ Acd m = vod vi c vi d iˆd ∆R voc ∆gm −R = voc ⇒ Ad cm = − vi d 22 2(1 + 2gmRSS ) 2 Di...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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