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Unformatted text preview: Q1 ∆Q1 S C L L Dummy Switch with Equalizing Capacitor Design the M2 dummy switch so that
W2 = W1
2 L2 = L1
∆Q1 = ∆Qov 1 + α∆QCH 1 1
∆Q2 = ∆Qov 1 + ∆QCH 1
2 • The problem is that α is not exactly 1/2.
S/H 17-12 Analog ICs; Jieh-Tsorng Wu Diﬀerential Sampling
Vi1 Vo1 − Vo2 = [Vi 1(1 + Vo1 M1
D Vi2 Vo2 M2 C C L VOS 1) + VOS 1 ] − [Vi 2(1 + 2) + VOS 2 ] = (Vi 1 − Vi 2)[1 + D ] + (Vi 1 + Vi 2) C + VOS
= Diﬀerential-Mode Gain Error
= Common-Mode Gain Error
= VOS 1 − VOS 2 = Oﬀset • The switching errors of M1 and M2 at Vo1 and Vo2 are to the ﬁrst order equal and
hence appear as a common-mode component at the output.
• Good CMRR and PSRR. Less sensitive to φ waveform.
• The body eﬀect can cause
S/H C = 0 as well as nonlinearity.
17-13 Analog ICs; Jieh-Tsorng Wu Bottom-Plate Sampling
φ The charge in C can be expressed as
M1 Vi Vo
Q1 QC (B) = C · Vi (kTs ) − ∆Q2 C
x φa Q2
M2 QC (C) = C · Vi (kTs ) − ∆Q2 + ∆Q1 ≈ C · Vi (kTs ) − ∆Q2
• The switching charge ∆Q2 is independent of Vi , and
contains little noise due to aperture jitter.
• Since node x is ﬂoating during period B and C, the
switching charge ∆Q1 ≈ 0. φ
kTs S/H QC (A) = C · Vi (t ) C • Parasitic capacitance from node x to ground can
enhance ∆Q1. 17-14 Analog ICs; Jieh-Tsorng Wu Complementary Analog Switches
V i A B
V V n
g DD p i V
gap V i
(Vg − Vs − Vt ) = β (Vg − Vt0 − nVs ) β = µCox
Vt = Vt0 + (n − 1)Vs
gn = βn[VDD − Vt0,n − nnVi ]
gp = βp[VDD − Vt0,p − np(VDD − Vi )] gon = µCox VDD(mi n) = nnVt0,p + npVt0,n
nn + np − nn np VDD(mi n) 2Vt0
2−n if nn = np and Vt0,n = Vt0,p • If VDD > VDD(mi n), no gap between gn and gp curves, thus conduction for any Vi is
possible by parallel connection of nMOST and pMOST.
S/H 17-15 Analog ICs; Jieh-Tsorng Wu A Diﬀerential BJT Sampling Switch
VCC Q3 Q4
CF CF R3 CF Q5 V o- Q6
V i+ CH R4 φ Q7 Q8 φ Q1 Q2 R1 V iR2 I1 I2 V o+ φ Q9 Q10 φ CH I2 VEE
S/H 17-16 Analog ICs; Jieh-Tsorng Wu A Diﬀerential BJT Sampling Switch
• The nonlinearities of Q1 and Q2 are canceled by Q3 and Q4.
• The diﬀerential operation results in only odd harmonics introduced by the Q5 and Q6
• During hold mode (φ = 0), Q5 and Q6 are in cut-oﬀ region, the feedthrough gain is
AH (Without CF ) ≈ Cj e5
CL + Cj e5 AH (With CF ) ≈ Cj e5
CL + Cj e5 CF
Cj e5 • Reference: P. Vorenkamp, et al., Fully Bipolar 120 MS/s 10-b Track-and-Hold Circuit,
JSSC 7/92, pp. 988–992. S/H 17-17 Analog ICs; Jieh-Tsorng Wu Open-Loop MOST S/H
A1 Vo M1
C Vi Vo A1
C H1 H2 H1 • M2 and CH 2 are used to compensate for the switching error of M1.
• The VOS of the opamp is shown in Vo.
• The aperture jitter can be reduced by having clock signals that change above and
below Vi by ﬁxed amounts.
S/H 17-18 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Miller Holding Capacitor
φ1 φ2 Sample Mode
M3 Vi M1
C Hold Mode Vi φ1 C H C H H M2
A1 Vo V1
A1 Vo V1
A1 VOS VOS φ1 = 1 Vo φ2 = 1 φ1
t1 S/H t2 17-19 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Miller Holding Capacitor
To consider the VOS eﬀect, let A1 = ∞ and Vi = 0, then
Vo(t1) = VOS (t1) Vo(t2) = VOS (t2) − VOS (t1) • The VOS is sampled in the sample mode, and canceled in the hold mode.
To consider the ﬁnite gain eﬀect, let VOS = 0, then during the hold mode,
Vo − V1 = Vi Vo = −A1V1 ⇒ Vo = Vi
1+A 1 ≈ Vi · 1 − 1
A1 • The Vo is reset to ground in sample mode. High slew-rate opamp is required.
• The virtual ground is not ideal at high frequencies in the sample mode.
• The switching errors are concerns.
S/H 17-20 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Miller Capacitor and Bottom-Plate Sampling Sample Mode
2 S4 S6
C Vi2 S/H 1
S2 L1 H2 S5 Vo1
C H1 1a VCMI Vi1 L2 H1 C
C L1 H1 H2 Vi2 φ1 = 1 Vo 1 Vo2 VCMI 17-21 L1 Vo1 C
C Hold Mode Vo 2
C C H2 L2 C L2 φ2 = 1 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Miller Capacitor and Bottom-Plate Sampling
• The opamp is open-loop during the sample mode. Glitches can occur during the
transition from the sample mode to the hold mode.
• VOS of the opamp is not canceled.
• The outputs, Vo1 and Vo2 , are precharged to Vi 1 and Vi 2 during the sample mode, so
that the settling time in the hold mode can be reduced.
• The input common-mode voltage, VCMI , can be diﬀerent from the value of (Vi 1 + Vi 2)/2.
• The VCMO of the opamp’s CMFB should closely follow the value of (Vi 1 + Vi 2)/2.
• The mismatches of the switching errors of S3–S8 can introduce a constant oﬀset
voltage in the outputs. S/H 17-22 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Double Miller Capacitors φ
Vi Sample Mode M1 φ
C a Vo
C H1 H2 Q1 Vi
C H1 A1 φ S/H C Vo
C H2 H1 C H2 Q2 M2 φ Hold Mode A1 φ=1 V1 A1 V2 φ=0 a 17-23 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Double Miller Capacitors
Let ∆Q2 be the charge injecting to V1 when M2 turns oﬀ. Then
∆Q2 = CH 1(∆V1 − ∆Vo)
⇒ ∆Vo ≈ ∆V2 = −A1∆V1 ∆Q2
1 + A1 CH 1 A1
∆Vo = −
1 + A1 CH 1 • ∆Q2 is independent of Vi .
Let ∆Q1 be the charge injecting to Vo when M1 turns oﬀ. Then
∆Q1 = CH 1(∆Vo − ∆V1) + CH 2(∆Vo − ∆V2)
⇒ ∆V1 ≈ ∆Vo ∆V2 = −A1∆V1 ≈ −A1∆Vo ∆Q1
1 + A1 CH 2 • Small CH 1 and CH 2 can be used. S/H 17-24 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Double Miller Capaci...
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