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Unformatted text preview: ﬀects of the opamp’s input oﬀset voltage and its 1/f noise.
• To minimize switching noises, realize switches with nMOSTs whenever possible, and
turn oﬀ the switches near the virtual ground node of the opamps ﬁrst.
• Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Eﬀects
of OpAmp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper
Stabilization,” Proc. IEEE, Nov. 1996, pp. 1584–1614. S/H 1741 Analog ICs; JiehTsorng Wu A CapacitiveReset SampledData Ampliﬁer
C a
2 C 3 C 3 3 S6
1a V S5 C 2 2
i C 1 2 C
1 S2
C V1
o 1
V 2 S4
S3
V S1 C 2 C V 1
V OS OS o V V1
i C V o 1
V OS 4 φ1 = 1 φ2 = 1 a φ1 a φ2 φ1
φ2
t1 S/H t2 t3 t4 1742 Analog ICs; JiehTsorng Wu A CapacitiveReset SampledData Ampliﬁer
To consider the VOS eﬀect, let A = ∞ and Vi = 0, then
V1(t1) = VOS (t1)
Vo(t2) = 1 +
Vo(t3) = VOS (t3) + Vo(t2) + C1
× VOS (t2) − VOS (t1)
C2 C2
C1 + C2
× VOS (t3) − VOS (t2) ≈ VOS (t3)
× Vo(t2) + 1 +
C3
C3 C1
× VOS (t4) − VOS (t3)
Vo(t4) = 1 +
C2
• During φ2 = 1, the eﬀects of opamp’s VOS and 1/f noise are reduce by CDS. S/H 1743 Analog ICs; JiehTsorng Wu A CapacitiveReset SampledData Ampliﬁer
To consider the ﬁnite gain eﬀect, let VOS = 0, then
−C1V1(t1) − C2V1 (t1) = C1[Vi (t2) − V1(t2)] + C2[Vo(t2) − V1(t2)]
⇒ Vo(t2) = − V1 = −Vo/A C1
C1
1
1
1
·
1+
× Vi (t2) +
× Vo(t1)
·
C2 1 + 1 1 + C1
A
C2 1 + 1 1 + C1
A
C
A
C
2 ≈− C1
(1 −
C2 1) 2 × Vi (t2) + C1
Vo(t3) ≈ (1 − 2)Vo(t2) + (1 −
C3
C1
Vo(t4) ≈ − (1 −
C2 1) 1 S/H − 1) × Vo(t1) C2
(1 −
2)Vi (t2) +
C3 × Vi (t4) + 1(1 − 1) C1
Vi (t2)
3)Vo (t2 ) ≈ Vo (t2 ) ≈ −
C2
× Vo(t3) C1
× [Vi (t4) − Vi (t2)] +
1
C2 C1
≈ − × Vi (t4) +
C2
C1
1
1+
=
A
C2 1 (1 2 C1
1
1+
=
A
C3
1744 3 2 C1
1C
2 × Vi (t2) C2
1
1+
=
A
C3
Analog ICs; JiehTsorng Wu A CapacitiveReset SampledData Ampliﬁer
• During φ2 = 1, the eﬀects of opamp’s VOS and 1/f noise are reduce by CDS.
2 • During φ2 = 1, the errors due to opamp’s ﬁnite gain, A, are proportional to 1/A for
lowfrequency input.
• During φ1 = 1, the output keeps the value obtained in the previous φ2 = 1 period.
• C4 is an optional deglitching capacitor used to provide continuoustime feedback
during the nonoverlap clock times. This capacitor would normally be small.
• The clock phases for S1 and S2 can be exchanged, to obtain noninverting gain.
• When CDS is used, the opamps should be designed to minimize thermal noise rather
than 1/f noise. S/H 1745 Analog ICs; JiehTsorng Wu A CapacitiveReset CDS Ampliﬁer
φ1 = 1
C C 2 1
V C 2 1 S5 A 2
C’
1 S7
V 2
i 1 V S3
V S1 C 1 C’
1 1 1a 1
S8 2 S4 2a o S9 S2
S10 2 S6 C
V 1746 C 2 1
V i o A
C’
1 S/H C’
2 i φ2 = 1
C’
2 o C’
2 Analog ICs; JiehTsorng Wu A CapacitiveReset CDS Ampliﬁer
• During φ1 = 1, C1 and C2 are used in the feedback network to have
Vo ≈ − C1
C2 · Vi but with errors due to VOS , 1/f noise, and A.
• During φ1 = 1, the opamp input voltage is sampled and stored in C1 and C2.
• During φ2 = 1, C1 and C2 are used in the feedback network, the output errors
due to VOS , 1/f noise, and A are canceled by the correlated doublesampling (CDS)
operation. S/H 1747 Analog ICs; JiehTsorng Wu Comparators and Oﬀset Cancellation Techniques JiehTsorng Wu ES A October 25, 2002 1896 National ChiaoTung University
Department of Electronics Engineering Comparators
Vi1 Vo Vi2 Typical Architecture
Vi1 Vo A Vi2 Latch Vo CLK
Vi1 Vi2
0 • A comparator compare the instantaneous values of two inputs generate a digital 1 or
0 level depending on the polarity of the diﬀerence.
• Usually a clock is applied to improve the performance. Comparators 182 Analog ICs; JiehTsorng Wu Comparator Design Considerations
• Resolution (gain).
• Accuracy (oﬀset).
• Input range (dynamic range).
• Commonmode rejection.
• Speed (conversion time, overdrive recovery).
• Power dissipation.
• Input kickback noise.
• Area Comparators 183 Analog ICs; JiehTsorng Wu Comparison with SinglePole Ampliﬁer
Vo
Vo Vi
Ao Vi R
g C U
t m Vi U= t Vo
Vi = Ao 1 − e−ta/(RC) ta
1
= Ao × ln τm
1− a Ao = gmR τm = U
Ao ⇒ ta
≈U
τm if U C
gm
Ao • The ampliﬁcation in a comparator need not be linear.
Comparators 184 Analog ICs; JiehTsorng Wu Comparison with MultiStage Cascaded Ampliﬁer
Vo1
Vi R
g Vo2 R C
g m Vi R C
g m V o1 ta
1
≈ (U × N !) N
τm Vo for ta C m V o(N−1) Aoτm • There exits an optimum number of cascaded stages for minimum ta.
• Optimum in N is very broad.
• Gain of √ Comparators 10 (i.e. 10 dB) per stage results in near optimum delay (within 10%). 185 Analog ICs; JiehTsorng Wu Comparison with PositiveFeedback Regeneration
Vo(t) Vo Vo1 Vo(0) Vo2
U C R g g m U= m Vo(ta)
Vo(0) R =e t C t (Ao −1)ta
RC ta
1
=
× ln(U )
1
τm 1 −
A Ao = gmR
⇒ o Comparators 186 τm = ta
≈ ln(U ) if
τm a C
gm
Ao 1 Analog ICs; JiehTsorng Wu Comparison with PositiveFeedback Regeneration
• The gain is not bou...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.
 Winter '09
 Choma
 Integrated Circuit, Transistor, The Land

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