Analog Integrated Circuits (Jieh Tsorng Wu)

Matching properties is 1 small voltage coecient no

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Unformatted text preview: e twin-tub processes that have separate and optimized wells for nMOSTs as well as pMOSTs. • Additional processing steps may be used to fabricate vertical bipolar transistors on the same chip. This is called a BiCMOS technology. Technologies 4-12 Analog ICs; Jieh-Tsorng Wu MOS Transistors • May have devices with different Vt . • Source/drain can be shared between two series-connected MOSTs of the same type. • Wide devices usually employ stacked layout. Technologies 4-13 Analog ICs; Jieh-Tsorng Wu Parasitic BJTs in CMOS Technologies Vertical PNP Transistor Lateral PNP Transistor E B C E p+ n+ p+ p+ C1 B C2 p+ VDD n+ p+ N-Well N-Well P-Substrate P-Substrate C2 C1 VSS VSS • The collector is usually in ring form surrounding the emitter. • In the lateral devices, the MOST’s L is the base width. • The ratio of IC2/IC1 is poorly controlled in practice. Technologies 4-14 Analog ICs; Jieh-Tsorng Wu Resistors in CMOS Technologies • n+ and p+ diffusion Polysilicon Resistor – 10–30 Ω/ • Polysilicon – 20–80 Ω/ • N (or P) well diffusion – 1k–10k Ω/ • MOSTs in the triode region – Depends on Vov and W/L • Large R variation due to process variation. • Matching properties is ∼1%. • Small voltage coefficient. • No parasitic pn junction. Technologies 4-15 Analog ICs; Jieh-Tsorng Wu Capacitors in CMOS Technologies • Poly-Poly Poly-Poly Capacitor • Poly-Metal • Metal-Metal (MIM) • Multi-Layer Sandwich. • Lateral structures. • MOSTs in triode region • Bottom-plate Cparasitic is 10%–30% of C itself. • MOS in accumulation • Matching properties is 0.1%–1%. – Large voltage coefficient. – Large R in one terminal. • Voltage coefficient is < 50 ppm/V. ◦ • Temperature coefficient is < 50 ppm/ C. Technologies 4-16 Analog ICs; Jieh-Tsorng Wu Matching Issues Mismatches between two supposedly identical devices are due to • Localized geometric variation. – Resulting from the limited resolution of the photolithographic process itself • Global material gradient variation. – Variations across wafer resulting from nonuniform conditions during the fabrication processes. • Temperature gradient variation. Technologies 4-17 Analog ICs; Jieh-Tsorng Wu Guidelines for Better Device Matching Device Considerations: • Match devices of equal nature. – e.g., no JFET-MOST pair or poly-diffusion resistor pair. • Devices to be matched should operate on the same temperature. • Input offset voltage for a BJT pair is only ∼1/10 that for a MOST pair. • May consider post-fabrication trimming. Technologies 4-18 Analog ICs; Jieh-Tsorng Wu Guidelines for Better Device Matching Local Matching Consideration: • Increase device size. • Round devices matches better than square devices. • Whenever possible, utilize series and/or parallel combination of unit-sized devices to form devices of different sizes. • Use dummy devices to protect matching devices from different etch effects. Technologies 4-19 Analog ICs; Jieh-Tsorng Wu Guidelines for Better Device Matching Global Matching Consideration: • Layout devices with the same orientation. • Decrease device separation distance. • Try a common-centroid layout for the devices to be matched. 1 M1 2 1 M2 2 Technologies 1 M2 2 1 M1 2 4-20 Analog ICs; Jieh-Tsorng Wu Transistor Pair Layout Example Technologies 4-21 Analog ICs; Jieh-Tsorng Wu Resistor Pair Layout Example Technologies 4-22 Analog ICs; Jieh-Tsorng Wu Capacitor Pair Layout Example Technologies 4-23 Analog ICs; Jieh-Tsorng Wu Capacitor Errors x e y Assume a rectangular capacitor with dimension x and y . Then Cideal = Cox · x · y Due to lithography modification ∆e, we have Ctrue = Cox · (x − 2∆e) · (y − 2∆e) ≈ Cideal · (1 − r Technologies r) x+y Perimeter = ∆e × = 2∆e × xy Area 4-24 Analog ICs; Jieh-Tsorng Wu Capacitor Layout Design To minimize capacitor ratio error, want • Capacitors of identical values should have the same shape. • Capacitors of different values should have the same perimeter-to-area ratio. Let unit-size capacitor Cu have a square layout with xu on each side. Want to realize a new capacitor C with dimension x and y so that C =K Cu and 1 Perimeter 2xu x + y = = 2 x·y 2 Area xu We have x·y 2 xu x+y = =K 2xu ⇒ y = xu K ± K2 − K 2 K xu x= y • K is usually between 1 and 2. Technologies 4-25 Analog ICs; Jieh-Tsorng Wu Analog Section Floor Plan Example Technologies 4-26 Analog ICs; Jieh-Tsorng Wu Noise-Coupling Layout Considerations • Want to minimize noise from digital circuits coupling into the substrate or analog power supplies. • Separate power lines for analog and digital circuits. • Different region for analog and digital circuitry, separated by guard rings and wells connected to the power supplies. • Use metals and wells as shield to protect sensitive nodes. The shields must be connected to clean supply voltages. • Whenever possible, bypass the power supplies with junction capacitors and/or MOSTs. Technologies 4-27 Analo...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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