Analog Integrated Circuits (Jieh Tsorng Wu)

Monotonicity is not guaranteed potentially large

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Unformatted text preview: 5 4 R S L 1+sR C L5 1+sR C S1 V SC Filters I C5 V 2 1/(sL2) V 5 C3 V -1/(sC 1) V L4 C1 0 4 3 L2 V V 2 1 S 1/R S V I V 1 23-51 5 V out Analog ICs; Jieh-Tsorng Wu An All-Pole Low-Pass SC Ladder Filter R V V 1 S 1 2 V 1 1 4 in C R C S 3 L 2 1 R L 4 C L 5 V V V 1 1 1 V 1 1 3 V 1 out 5 2 in C V S 2 C 1 2 2 S C 1 1 C 1 2 C C C 1 V 4 C 2 2 C 1 1 3 C 2 2 C 4 1 L C 5 2 1 V 2 V SC Filters 1 C 1 C V 2 3 23-52 C 1 C out 2 V 5 Analog ICs; Jieh-Tsorng Wu SC Ladder Filter Using Signal-Flow Graph Inverting BE Integrator Noninverting FE Integrator C=1 C=1 K 11 Vi 2 1 1 1 Vo K 11 Vi 2 2 2 1 1 Vo 1 −1 z HF E (z ) = +K · 1 − z −1 1 HBE (z ) = −K · 1 − z −1 • HBE (z ) is a Backward-Euler (BE) integrator. HF E (z ) is a Forward-Euler (FE) integrator. • The phase errors of the integrators are cancelled in the ladder topology, while the magnitude errors can cause deviations in the frequency response when ωTs 1 is no longer true. • The SC ladder filters are inherently time-staggering. SC Filters 23-53 Analog ICs; Jieh-Tsorng Wu SC Ladder Filters Design Methodology It is possible to realize the SC ladder filters with exact frequency response, using only the BE and FE integrators. The design procedures involves bilinear transformation prewarping and frequency-dependent impedance scaling. sTs s Ts z 1/2 − z −1/2 = = tanh λ= 1/2 + z −1/2 2 2 z sTs sTs 1 1/2 1 1/2 −1/2 −1/2 µ= = sinh = cosh γ= z −z z +z 2 2 2 2 γ µ2 − γ 2 = 1 z 1/2 = µ + γ ⇒ λ= µ • λ ↔ z is the bilinear (BL) transformation. • γ ↔ z is the lossless discrete (LD) transformation. • The design goal is to implement H z = e with SC integrators. SC Filters sTs 23-54 with H (γ ). H (γ ) can then be realized Analog ICs; Jieh-Tsorng Wu SC Ladder Filters Design Procedures 1. Prewarp the filter specifications from ω to ω with bilinear transformation. ωTs 2 ω = tan 2 Ts 2. Find H (s ). Renormalize H (s ) into H (λ) by setting s Ts /2 = λ. 3. Realized H (λ) as an LC ladder filter in λ domain. 4. Scale the impedance level, Y (γ ) = µY (λ) Z (γ ) = Z (λ)/µ to obtain the γ -domain LC ladder circuit. 5. Implement the γ -domain circuit with SC circuits. SC Filters 23-55 Analog ICs; Jieh-Tsorng Wu Nyquist-Rate Digital-to-Analog Converters Jieh-Tsorng Wu ES A July 16, 2002 1896 National Chiao-Tung University Department of Electronics Engineering A/D and D/A Interfaces x(t) A/D Interface x(n) Digital Processor y(n) D/A Interface y(t) Analog World Analog-to-Digital Interface x(t) Low-Pass Filter x(n) Sampling Circuit Quantizer Decoder fs Digital-to-Analog Interface y(n) Deglitcher fs DACs D/A Converter Inverse-Sinc / Low-Pass Filter y(t) fs 24-2 Analog ICs; Jieh-Tsorng Wu Continuous-to-Discrete Conversion xc (t) Analog Prefilter x(n) yd (t) y(n) Discrete Time Processing Sampling y (t) c Analog Postfilter DAC Ts Xc(j Ω) xc (t) A Ω t 0 Ts 2Ts 3Ts 0 Ωb Ωs 2Ωs X ej ω x(n) A Ts n 0 DACs 1 2 3 0 24-3 2π 4π ω Analog ICs; Jieh-Tsorng Wu Discrete-to-Continuous Conversion yd (t) Yd (j Ω) A Ω t Ts 3Ts 2Ts 0 yc (t) Ωs 2Ωs Yc(j Ω) A Ω t 0 Ts 3Ts 2Ts 0 Ωs 2Ωs 1 Ω sinc π Ω s Ω 0 DACs 24-4 Ωs 2Ωs Analog ICs; Jieh-Tsorng Wu Discrete-to-Continuous Conversion The digital-to-analog converter (DAC) usually performs the discrete-to-continuous sample-and-hold translation, i.e., ∞ yd (t ) = y (n) · (t − nTs ) (t ) = where n=−∞ 1 0 if 0 < t < Ts otherwise The continuous-time Fourier transform (CTFT) of yd (t ) can be expressed as Yd (j Ω) = Yd (z )|z=ej ΩTs × Hd a(j Ω) = Yd ej ω ω=ΩTs × Hd a(j Ω) The discrete-to-continuous sample-and-hold transfer function is 1 − e−sTs Hd a(s) = s Hd a(j Ω) = e Ωs = 2πfs = DACs −j πΩ/Ωs 2π Ts 24-5 sinc(x ) = Ω · Ts · sinc π Ωs sin x x Analog ICs; Jieh-Tsorng Wu Imperfections in Discrete-to-Continuous Conversion The D/A conversion of y (n) can be expressed as: ∞ yd (t ) = ˆ y (n) · C[t − nTs + ] n=−∞ ˆ • The y (n) → y (n) conversion may contains gain error, offset, and nonlinearity. • C(t ) has transient behavior. Its pulse width can be larger than Ts . • C(t ) may contain y (n) dependency. – A return-to-zero C(t ) can reduce the y (n) dependency. • The timing jitter DACs can be random or deterministic. 24-6 Analog ICs; Jieh-Tsorng Wu D/A Transfer Characteristic (Digital Input) bN-1 b1 Ao b0 AFS AF S = Full-Scale Output AFS D/A 2 ∆ = LSB = Step Size = Ao (Analog Output) 0 000 100 111 Din AF S 2N Ao = ∆ × Di n = ∆ × bN −12N −1 + · · · + b121 + b020 = AF S × bN −12−1 + · · · + b12−(N −1) + b02−N • In some applications, relationship between Di n and Ao can be nonlinear. • Di n may use other coding scheme such as offset binary or 2’s complement. DACs 24-7 Analog ICs; Jieh-Tsorng Wu D/A Transfer Characteristic Nonmonotonic Offset Ao Gain Error Ao Ao Ideal Din Din AOS 0 0 DACs Din 0 Offset Error = Gain Error = Ideal AOS ∆ Ao,max − AOS ∆· (2N − 1) 24-8 AOS = Ao|Di n=0 = Ao,max − AOS AF S · (1 − 2−N ) Analog ICs; Jieh-Tsorng Wu D/A Nonlinearity Ao Ao Ao INL DNL Large INL Low DNL 0 Din Din 0 DNL=-1LSB Din 0 • Measure of deviation from straight line with offset and gain error corrected. • Differential nonlinearity (DNL): Maximum deviation of the analog output step from the ideal value of 1 LSB (= ∆). • Integral nonlinearity (INL): Maximum deviation of the analog output from the ideal value. DACs 24-9 Analog ICs; Jieh-Tsorng...
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