Analog Integrated Circuits (Jieh Tsorng Wu)

Plls 27 5 analog ics jieh tsorng wu second order pll

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Unformatted text preview: ng Wu Noise-Shaped Dithering for Multi-Stage Cascaded Modulators d x(k) z 1 (k) 1 z 1 y (k) 1 1 z z 1 y(k) 1 D/A e 1 d (k) z 2 (k) y (k) 2 1 1 z 1 1 z 1 D/A −1 Y1 = z X + 1 − z −1 2 E1 + 1 − z Y = z − 1 Y1 − 1 − z − 1 Oversampling 2 −1 3 D1 Y2 = z −1E1 + 1 − z −1 E2 + 1 − z −1 D2 Y2 = z − 2 X + z − 1 1 − z − 1 26-35 3 D1 − 1 − z −1 3 D2 Analog ICs; Jieh-Tsorng Wu Multi-Bit ∆Σ Modulator e(k) A/D Converter x(k) y(k) G(z) F(z) D/A n(k) e(k) D/A Converter y(k) x(k) G(z) y(t) D/A n(t) F(z) Oversampling 26-36 Analog ICs; Jieh-Tsorng Wu Multi-Bit ∆Σ Modulator For the A/D converter G (z ) F (z )G (z ) 1 Y (z ) = X (z ) + E (z ) − N (z ) 1 + F (z )G (z ) 1 + F (z )G (z ) 1 + F (z )G (z ) ≈ ST F (z )X (z ) + NT F (z )E (z ) − N (z ) • Out-of-band noise is reduced. Requirements for the analog circuitry are less severe. • Since they have better stability, more aggressive noise transfer functions may be used. • The DAC linearity errors are not shaped. The DAC must be nearly as linear as the complete converter. Oversampling 26-37 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Dynamic Element Matching Unit Elements M M v Randomizer Ao 2 Analog Output 1 Ao v 0 Oversampling 1 2 26-38 3 4 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Dynamic Element Matching No Scrambling Random Scrambling Signal Signal n n freq freq • For any value of v , the averaged error in Ao is zero. • Whitens the mismatch noise. • The randomizer may consists of a thermometer-type encoder, a random-number generator, and a switchbox. Butterfly structure is often used to simplified the switchbox design. • Reference: Ian Galton, “A Rigorous Error Analysis of D/A Conversion with Dynamic Element Matching,” Tran. on Circuits and Systems–II, pp. 763–772, 12/95. Oversampling 26-39 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Data-Weighted Averaging M v(k) DWA Selector M Ao 2 Analog Output 1 v(1)=3 v(2)=4 v(3)=2 DWA Scrambling Signal n freq Oversampling 26-40 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Data-Weighted Averaging • Once every element in the array has been used, the cumulative error is zero. The errors induced by the use of each element are averaged out as soon as possible. • Reference: R. Baird and T. Fiez, “Linearity Enhancement of Multibit ∆Σ A/D and D/A Converters Using Data Weighted Averaging,” Tran. on Circuits and Systems–II, pp. 753–762, 12/95. Oversampling 26-41 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Noise-Shaped Scrambler Swapper Cells Unit Elements 4 v(k) 3 Therm. Code 2 1 Ao Analog Output • Each swapper tries to equalize the activity of each of its outputs. Each output from the scramble is a first-order noise-shaped sequence. • Reference: R. Adams, et al, “A 113dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling,” ISSCC, pp. 62–63, 2/98. Oversampling 26-42 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC v Element Selection Logic sy su min() sx se H 2 (z) − 1 Vector Quantizer sv M de Oversampling M M Unit Elements 26-43 Ao Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC • The element selection logic (ESL) is a collection of M digital ∆Σ modulators, each possessing a NT F (z ) equal to H2(z ), implemented with the error feedback structure and supplied with a common input. • The vector quantizer uses information in the sy vector to select which v elements to enable. Want to minimize se = sv − sy. • The sy = sx − min(sx) · [11 · · · 1] function is a shifting operation which set the minimum component in sy to zero. The purpose is to reduce the magnitude of sy vector, in a manner that does not disturb the noise-shaping property of the selection logic. Oversampling 26-44 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC Let de = [e1, e2, · · · , eM ] be the DAC error vector. T T • By definition, de · [0] = 0 and de · [1] = 0, where [0] = [00 · · · 0] and [1] = [11 · · · 1]. T T T • de · (sv1 + sv2) = de · sv1 + de · sv2 T T • de · sv + de · sv = 0 For the error-feedback structure, we have SV(z ) = SU (z ) · [1] + H2(z ) · SE(z ) Oversampling 26-45 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC The vector quantizer obeys SV(z ) · [1]T = V (z ) The analog output is SV(z ) · ([1] + DE)T SV(z ) · [1]T + SV(z ) · DET = V (z ) + SU (z ) · [1] · DET + H2(z ) · SE(z ) · DET = Oversampling = = Ao(z ) V (z ) + H2(z ) SE(z ) · DET 26-46 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC — First-Order Example H2(z ) = 1 − z−1 M=4 sv(k ) = VQ[sy(k )] k 0 1 2 3 4 5 6 v (k ) 1 1 1 2 0 4 2 T se(k ) = sv(k ) − sy(k ) sy(k ) 1, 1, 1, 1 0, 1, 1, 1 0, 0, 1, 1 0, 0, 0, 1 0, 1, 1, 1 0, 1, 1, 1 0, 1, 1, 1 sv(k ) 1, 0, 0, 0 0, 1, 0, 0 0, 0, 1, 0 1, 0, 0, 1 0, 0, 0, 0 1, 1, 1, 1 0, 1, 1, 0 sx(k ) = −se(k − 1) se(k ) +0, −1, −1, −1 +0, +0, −1, −1 +0, +0, +0, −1 +1, +0, +0, +0 +0, −1, −1, −1 +1, +0, +0, +0 +0, +0, +0, −1 sx(k ) −0, +1, +1, +1 −0, −0, +1, +1 −0, −0, −0, +1 −1, −0, −0, −0 −0, +1, +1, +1 −1, −0, −0, −0 −0, −0, −0, +1 T • Si...
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