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Analog Integrated Circuits (Jieh Tsorng Wu)

Reference h s lee jssc 1284 pp 813819 adcs 25 26

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Unformatted text preview: of Electronics Engineering A/D and D/A Interfaces x(t) A/D Interface x(n) Digital Processor y(n) D/A Interface y(t) Analog World Analog-to-Digital Interface x(t) Low-Pass Filter x(n) Sampling Circuit Quantizer Decoder fs Digital-to-Analog Interface y(n) Deglitcher fs ADCs D/A Converter Inverse-Sinc / Low-Pass Filter y(t) fs 25-2 Analog ICs; Jieh-Tsorng Wu Continuous-to-Discrete Conversion xc (t) Analog Prefilter x(n) yd (t) y(n) Discrete Time Processing Sampling y (t) c Analog Postfilter DAC Ts Xc(j Ω) xc (t) A Ω t 0 Ts 2Ts 3Ts 0 Xe x(n) Ωb Ωs 2Ωs jω A Ts n 0 ADCs 1 2 3 0 25-3 2π 4π ω Analog ICs; Jieh-Tsorng Wu A/D Quantization Characteristic Do (Analog Input) 111 Ai 100 Quantizer Ai 000 A b N-1 b 1 b 0 Quantization Error FS /2 A FS Q (Digital Output) 1/2 Ai 1/2 N −1 Ai ,tran = ∆ × i =0 AF S = Full-Scale Output ADCs 1 bi 2i − ∆ 2 ∆ = LSB = Step Size = 25-4 AF S 2N Analog ICs; Jieh-Tsorng Wu Imperfections in A/D Quantization Characteristic Offset Do Gain Error Ideal Do Nonlinearity Ideal Ai Ai Do Ideal Ai • Differential nonlinearity (DNL): Maximum deviation in step width (width between transitions) from the ideal value of 1 LSB (= ∆). • Integral nonlinearity (INL): Maximum deviation of the step midpoints from the ideal step midpoints. Or the maximum deviation of the transition points from ideal. • If DNL = −1 LSB ⇒ missing code. ADCs 25-5 Analog ICs; Jieh-Tsorng Wu Quantization Noise x(k) x(t) fs N-Bit Quantizer y(k) Probability Density Function (pdf) e(k) e x(k) /2 /2 y(k) e(k ) is a quantization noise due to the quantization process. e(k ) ≡ y (k ) − x (k ) ADCs Noise Power = Pn = 25-6 e2pdf(e)d e = 12 ∆ 12 Analog ICs; Jieh-Tsorng Wu Quantization Noise Let the input x (k ) be a sinusoidal waveform 1 Signal Power = Ps = A2 2 x (k ) = A sin(2πfi · kTs ) The signal-to-noise ratio of y (k ) is Ps 2 A SNR ≡ =6· Pn ∆2 When the input’s amplitude A = AF S /2, the SNR reaches its maximum value. AF S = 2N ∆ Ps = 1 2N 2 ·2 ∆ 8 SNRmax = 22N × 3 = N × 6.02 dB + 1.76 dB 2 • The ratio between fs and fi should be irrational. • In the discrete-time domain, noise power of e(k ) is assumed to be uniformly 2 distributed between −Ωs /2 and +Ωs /2. The power density is ∆ /(12Ωs ). ADCs 25-7 Analog ICs; Jieh-Tsorng Wu Sampling-Time Uncertainty (Aperture Jitter) t V x(t) x(k) t fs kTs x (k ) = x (kTs + ∆t ) Ts = 1 fs For a full-scale sinusoidal input 1 x (t ) = AF S sin(2πfi t ) 2 1 dx × ∆t < AF S · πfi × ∆t < ∆ ∆V ≈ 2 dt ADCs 25-8 AF S = 2N ∆ ⇒ 1 1 ∆t < · N 2πf 2 i Analog ICs; Jieh-Tsorng Wu Sampling-Time Uncertainty (Aperture Jitter) Let x (t ) = 1 AF S sin (2πfi t ) and ∆t be a random variable, then 2 dx (t ) 1 x (k ) = x (kTs + ∆t ) ≈ AF S sin(2πfi kTs ) + 2 dt × ∆t t=kTs 1 ≈ AF S sin(2πfi kTs ) + AF S πfi cos(2πfi kTs ) × ∆t 2 1 1 x 2(k ) = A2 S + A2 S π2fi2 × ∆t 2 = Ps + Pn 8F 2F The signal-to-noise ratio of x (k ) is Ps 1 SNR = = = −20 log (2πfi · ∆trms) dB Pn 4π2f 2 · ∆t 2 i • If fi = 1 MHz, N = 14, SNR = 86 dB, want ∆trms < 8.0 psec. • If fi = 100 MHz, N = 10, SNR = 62 dB, want ∆trms < 1.26 psec. ADCs 25-9 Analog ICs; Jieh-Tsorng Wu DFT Nonlinearity Test of ADCs x(k) x(t) N-Bit Quantizer fs y(k) DFT SINAD (dB) y(t) Power Spectrum dBm/Hz 10 Bit 60 55 SFDR 50 fi 2fi 3fi f 9 Bit 8 Bit 45 40 -25 -20 -15 -10 -5 0 Input Level Relative to Full Scale (dB) ADCs 25-10 Analog ICs; Jieh-Tsorng Wu DFT Nonlinearity Test of ADCs • The ratio between fs and fi should be irrational. • In the discrete-time domain, noise power of e(k ) is assumed to be uniformly distributed between −Ωs /2 and +Ωs /2. The power density is ∆2/(12Ωs ). • The spurious free dynamic range (SFDR) is the ratio of the fundamental signal component to the largest distortion component when A = AF S /2. • The signal-to-noise plus distortion ratio (SINAD) is the ratio of power of the fundamental signal to the total power of noise and distortion when A = AF S /2. • In finding the total noise power, the noise bandwidth need to be specified. ADCs 25-11 Analog ICs; Jieh-Tsorng Wu Code Density Test of ADCs H(i) x(k) x(t) fs N-Bit Quantizer y(k) Histogram Do x(t) t Do W(i) Ai ADCs 25-12 Analog ICs; Jieh-Tsorng Wu Code Density Test of ADCs Let Nt be the total number of samples, H (i ) the number of counts in the i -th Do, and P (i ) the ideal probability for the i -the Do. We have W (i ) 1 H (i ) 1 = Ai +1,tran − Ai ,tran · = · ∆ ∆ Nt P (i ) • For high precision, sinusoidal waveform is usually for the input. The probability density p(V ) for A sin(ωt ) is 1 p(V ) = π A2 − V 2 • To test a 12-bit ADC, for 99 percent confidence and 0.10 bit precision, 4.2 million samples are needed. • Reference: Doernberg, JSSC 12/84, pp. 820–827. ADCs 25-13 Analog ICs; Jieh-Tsorng Wu Serial (Integrating) Architectures S2 C1 R1 Vi Vref Do S1 Vi RC ADCs Counter fc Vx T1 Control Logic Vx T2 t Vref RC 25-14 Analog ICs; Jieh-Tsorng Wu Serial (Integrating) Architectures The output is Do Vi = T2 = T1 · fc Vref • Linear search of possible subregions. • Integrating types: single slope, dual slope, quad-slope. N • Low conversion rate. Requires 2 × 2 clock cycles for a full-scale conversion. • The input is integrated in the T1 period, resulting in a filer transfer function of sin(πT1f ) |H (f )| =...
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