Analog Integrated Circuits (Jieh Tsorng Wu)

Reference u k moon et al jssc 1293 pp 12541264 gm c

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Unformatted text preview: section sequence in the order of increasing Qp is often close to the optimum. • It is often desirable to have a low-pass or bandpass biquad as the first section to minimize slew-rate problem. • If possible, employ a high-pass or band-pass biquad as the last section to eliminate low-frequency noise and dc offset. Active-RC Filters 21-23 Analog ICs; Jieh-Tsorng Wu Cascaded Filter Design Procedures 3. Gain Assignment. Every Vo,i should be as large as possible, i.e., M (Vo,1 ) = M (Vo,2 ) = · · · = M (Vo) Since i Hi (s) = i i ki ti (s) = j =1 ki j =1 Filter Specification i Ki = ti (s) j =1 → i Mi = max kj j =1 tj (j ω) j =1 H (s) = Hn(s) → K = Kn M = Mn We have Ki · Mi = Kn · Mn = K · M ⇒ Active-RC Filters i = 1, · · · , n − 1 M k1 = K · M1 Mi − 1 and ki = 21-24 Mi i = 2, · · · , n − 1 Analog ICs; Jieh-Tsorng Wu Cascaded Filter Design Procedures Active-RC Filters 21-25 Analog ICs; Jieh-Tsorng Wu High-Order Filter Using the Follow-the-Leader Feedback Topology R F,n R F,2 R F,1 R F,0 Ri Vi T2(s) T1(s) V0 Tn(s) V2 V1 Vn R o,n R o,2 RA Vo R o,1 R o,0 Active-RC Filters 21-26 Analog ICs; Jieh-Tsorng Wu High-Order Filter LC Ladder Simulation R V S V I S Y2 1 1 Z1 Y4 Z3 V Y(n-1) Z(n-2) 2 R Z(n) L Lossless LC Network A Fifth-Order Elliptic Low-Pass Filter R V S V V 1 R S Active-RC Filters 2 21-27 L Analog ICs; Jieh-Tsorng Wu High-Order Filter LC Ladder Simulation • Minimum passband sensitivity to component tolerances. • Can be implemented with – Element substitution. – Operational simulation with signal-flow graph. • Requires more opamps than the cascade and MF methods. Active-RC Filters 21-28 Analog ICs; Jieh-Tsorng Wu LC Ladder Simulation R V Y2 S Z1 S Y4 Y n-1 Z3 Z n-2 I k-1 V k-2 I k-2 Z k-2 V k-1 Y k-1 V k-2 Active-RC Filters Y k-1 R L I k+1 Vk Ik Zk V k+1 V k+2 Y k+1 I k+2 Z k+2 I k+1 I k-1 Z k-2 Zn Zk Vk 21-29 Y k+1 I k+3 Z k+2 V k+2 Analog ICs; Jieh-Tsorng Wu LC Ladder Simulation I k-1 Z k-2 Y k-1 V k-2 I k+1 Zk Y k+1 I k+3 Z k+2 V k+2 Vk Leapfrog (LF) Topology Z k-2 Active-RC Filters Zk Y k-1 21-30 Y k+1 Analog ICs; Jieh-Tsorng Wu An All-Pole Low-Pass Ladder Filter I V R in V 0 V I V -1/(sC 3) I C5 V 2 1/(sL2) V 5 C3 V -1/(sC 1) V L4 C1 0 4 3 L2 V -1/(sC 5) R 6 4 1/(sL4) out in 1/R L V V 1 V 1/R S R V 3 V 2 out 5 4 R S L 1+sR C L5 1+sR C S1 V Active-RC Filters L 6 in V V 2 1 S 1/R S V I V 1 21-31 5 V out Analog ICs; Jieh-Tsorng Wu An All-Pole Low-Pass Ladder Filter R V 1 S V 1 2 1 V 4 1 in C R S C 3 L 2 1 L 4 R C L 5 V V 1 1 V 1 3 1 V 1 out 5 • Component scaling can be done by maintaining the RC values. • Use both lossless and lossy integrators. • Combining the phase-lag Miller inverting integrator with the phase-lead noninverting integrator can reduce phase errors. Active-RC Filters 21-32 Analog ICs; Jieh-Tsorng Wu Signal-Level Scaling in Ladder Filters V0 T0(s) Vi V’0 V2 T1(s) T2(s) V1 K0 Vj = Hj (s) · Vj −1 T3(s) V3 α1 1/α2 T0(s) Vo Vi K1 Vj = αj Hj (s) · Vj −1 V’1 ⇒ α3 T3(s) T2(s) T1(s) 1/α1 V’2 α2 Vj = Vj · αj · 1/α3 V’3 Vo Vj −1 Vj −1 • The signal level of Vj can be scaled by αj . • Signal-level scaling is to maximize dynamic range. Want max|Vj (j ω)| = Vo,max for j = 0, · · · , n 0<ω<∞ • Scale Vj sequentially from j = 1 to j = n. Active-RC Filters 21-33 Analog ICs; Jieh-Tsorng Wu General Ladder Branches Series Branch Shunt Branch I1 L4 V1 I3 V2 V3 R0 L1 C2 L3 C3 C4 I2 R0 C1 L2 For the series branch I2 = (V1 − V3 ) · Y (s) = (V1 − V3) · 1 1 R0 + sL1 + sC + 2 1 1 sC3 + sL 4 For the shunt branch V2 = (I1 − I3) · Z (s) = (I1 − I3) · 1 1 G0 + sC1 + sL + 2 Active-RC Filters 21-34 1 1 sL3 + sC 4 Analog ICs; Jieh-Tsorng Wu General Ladder Branches by Active-RC Implementation C4 R=1 R=1 C3 R=1 R=1 C2 R=1 Ra V1 R=1 C1 R0 Rb V3 V2 V3 V1 1 · V2 = − − Ra Rb G0 + sC1 + 1 + sC 2 Active-RC Filters 21-35 1 1 sC3 + sC 4 Analog ICs; Jieh-Tsorng Wu Finite Transmission Zeros in the Series Branches I0 V1 C1 I0 V3 L2 I2 V1 V3 L2 C1 C2 s C2V3 1 C3 C2 C2 I4 1 V0 I4 C1 C2 L2 C2 V2 1 1 V4 C3 C2 C3 C2 s C2V1 1 V1 1 1 V3 1 I0 = sC1 V1 + (sC2 + Y2)(V1 − V3) = s(C1 + C2)V1 − sC2V3 − Y2(V1 − V3 ) I4 = (sC2 + Y2)(V1 − V3 ) − sC3 V3 = Y2(V1 − V3) + sC2 V1 − s(C2 + C3)V3 Active-RC Filters 21-36 Analog ICs; Jieh-Tsorng Wu MOST-C and Gm-C Filters Jieh-Tsorng Wu ES A July 16, 2002 1896 National Chiao-Tung University Department of Electronics Engineering MOSTs in the Triode Region VG VK VG VD V0 VS Allowalbe Operating Range ID VB VQ VB 2 γ +γ VK = VF B + φ0 − 2 γ2 VGB − VF B + 4 VF B = Flat-Band Voltage φ0 = Surface Band Bending ≈ 2φf γ = Body Effect Coefficient k = µCox W L VQ ← Model Accuracy Consideration ID 3 3 12 2 2 VDB − VSB − γ (VDB + φ0) 2 − (VSB + φ0) 2 = (VGB − VF B − φ0)(VDB − VSB ) − 2 3 k = (VGB − VF B − φ0)VDS − [f (VDB ) − f (VSB )] 3 3 12 2 1 2 2 2= (VX 0 + V0B ) + γ (VX 0 + V0B + φ0) 2 f (VX B ) = VX B + γ (VX B + φ0) 2 3 2 3 Gm-C Filters 22-2 Analog ICs; Jieh-Tsorng Wu MOSTs in the Triode Region Using Taylor’s series 3 1 2 12 12 2 + γ (V 2 V0B + V0B · VX 0 + VX 0 + γ (V0B + φ0) f (VX B ) ≈ 0B + φ0) · VX 0 2 2 3 1 3 1 1 3 2 + γ (V0B + φ0)− 2 · VX 0 − γ (V0B + φ0)− 2 · VX 0 + · · · 4 24 We have ID 1 = (VG 0 − VT )VDS − g(VD0 ) − g(VS 0 ) VT = VF B + φ0 + γ (V0B + φ0)...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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