Analog Integrated Circuits (Jieh Tsorng Wu)

Sc filters 23 32 analog ics jieh tsorng wu periodic

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Unformatted text preview: a (n + 1) − Vo(n + 1)] C ⇒ Vo(z ) = − C1 [Vi 1(z ) − Vi 2(z )] − 2 C 1 1 + A 1 + C1 + 2 • Must keep Cp1 C1 and Cp1,p3 Cp1 C2 + Cp3 C2 Cp1 V (z ) C2 i 1 ×z −1 1 − z −1 1 + A 1 + Cp3 C2 C2. – Connect the top plates of the capacitors to the opamp’s input. – Let the bottom plates of the capacitors always be driven. SC Filters 23-8 Analog ICs; Jieh-Tsorng Wu Parasitics-Insensitive SC Integrators C2 2 1 Vo φ1 φ2 C1 Vi2 2 1 Vo(z ) = n-1 Vi1 n n-1/2 C 2 n+1/2 −1 C1 C2 1 1 + A 1 + C1 + n+1 −Vi 1 + z Vi 2 Cp1 C2 + Cp3 C2 1 − z −1 1 + A 1 + Cp3 C2 • Insensitive to parasitics if A → ∞. • The two inputs have different delays. SC Filters 23-9 Analog ICs; Jieh-Tsorng Wu Fully Differential SC Integrators Vi2 2 1 Vi1 C1 2 VCMI 1 2 C2 1 Vo Vo Vi 1 = Vi 1+ − Vi 1− Vi 2 = Vi 2+ − Vi 2− Vo = Vo+ − Vo− C2 C1 Vi2 2 1 Vi1 −1 C1 1 z Vo(z ) = ×− · Vi 1 + · Vi 2 −1 −1 C2 1−z 1−z • VCMI and VCMO can be different. SC Filters 23-10 Analog ICs; Jieh-Tsorng Wu MOST Analog Switches C2 Vi C1 1 MOST Switch Model R on a 1 Vi Vo Vo 1 C1 Vo a 2 2 1 VCMI 1 µCox (W/L)Vov VDD Vi VSS C Ron = C2 a 1 VDD Vo C a 2 2 Vi VCMI Ts VSS mTs VCMI For good settling, want mTs > 5RonC = SC Filters 5C µCox (W/L)Vov 23-11 Analog ICs; Jieh-Tsorng Wu MOST Analog Switches • When turning off the switch, the switching error is ∆V = The maximum clock rate is αQCH C = αW LCox Vov C m µ∆V fs < · α 5L2 • Realize switches connected to VSS or near VSS with nMOSTs. • Realize switches connected to VDD or near VDD with pMOSTs. • Turn off the switches near the virtual ground node of the opamps first. • The thermal noise is proportional to kT /C. • There are also noises from the power supplies. SC Filters 23-12 Analog ICs; Jieh-Tsorng Wu Effects of Opamp’s Finite DC Gain C2 Vi C1 1 2 Vo(n) = −kVi (n) + Vo(n − 1) 1 2 If Ao = ∞, then Vo k H (z ) = − 1 − z −1 C1 k= C2 Ao If Ao = 1/µ is finite, then Vo(n) = −kαVi (n) + βVo(n − 1) 1 α= ≈ 1 − (1 + k )µ = 1 + ∆α 1 + (1 + k )µ 1+µ β= ≈ 1 − kµ = 1 + ∆β 1 + (1 + k )µ SC Filters 23-13 H (z ) = − kα 1 − βz −1 ∆α = −(1 + k )µ ∆β = −kµ 1 1 Analog ICs; Jieh-Tsorng Wu Effects of Opamp’s Finite DC Gain The transfer function H (z ) in s-domain is H (ej ωTs ) ≈ − k 1 − z −1 m(ω) ≈ ∆α − × [1 + m(ω)]ej θ(ω) z =ej ωTs ∆β 1 C1 1 ≈− 1+ · 2 2 C2 Ao C1 1 ∆β 1 1 1 1 C1 1 · θ (ω) ≈ − · · · · ≈· ≈ 2 tan(ωTs /2) 2 C2 Ao tan(ωTs /2) C2 Ao ωTs j ωi Ts • At the unit-gain frequency ωi , where H (e −m(ωi ) ≈ θ (ωi ) ≈ 1/Ao ) = 1, we have if ωi Ts /2 1 • In most applications, the magnitude error m(ω) has negligible effect, but the phase error θ (ω) can be detrimental in narrowband (high-Q) filters. SC Filters 23-14 Analog ICs; Jieh-Tsorng Wu Effects of Opamp’s DC Offset C2 Vi C1 1 2 1 Vo 2 VOS C1 1 C1 1 Vo(z ) = − · V (z ) + · V + VOS C2 1 − z −1 i C2 1 − z −1 OS • The VOS to Vo transfer function is also an integration. • When the entire filter is considered, the VOS may cause finite dc level shift in this and other integrators. SC Filters 23-15 Analog ICs; Jieh-Tsorng Wu An Offset Auto-Zeroing Scheme C2 3 Vi C1 1 2 1 C3 3 2 Vo 3 VOS φ1 φ2 φ3 • During the φ3 auto-zeroing mode, opamp’s offset voltage is stored in C3. SC Filters 23-16 Analog ICs; Jieh-Tsorng Wu Effects of Opamp’s Finite Settling Time T1 φ1 C2 φ2 Vi C1 1 2 1 2 Vo A Vo t settle t slew • Let tslew = 0, A(s) = ωu/s, T1 = Ts /2, ωi is the unit-gain frequency of the integrator, and ωi Ts 1. At ω = ωi , the magnitude error and phase error of the integrator are m(ωi ) ≈ θ (ωi ) ≈ −ωi Ts e−ωuTs /2 • Want ωu ≥ 5 · ωs . However, to avoid unnecessary noise aliasing, ωu should not be too much larger than necessary. SC Filters 23-17 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS C2 Vi C1 1 1 C’2 φ1 2 Vo 2 φ2 Ao 2 t1 VOS φ1 = 1 C1 φ2 = 1 C2 C’2 C1 t2 t3 C2 C’2 Vo Vo VOS SC Filters VOS 23-18 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS Consider the VOS effect only. Let Vi = 0 Ao = ∞ and ∆VOS (t ) = VOS (t ) − VOS (t − Ts /2) At t = t2 Vo(t2) = Vo(t1) + VOS (t2) + 1+ C2 C2 ∆VOS (t2) At t = t3 C1 ∆VOS (t3) Vo(t3) = Vo(t2) − VOS (t2) + 1 + C2 = Vo(t1) + ∆VOS (t2) + 1 + SC Filters 23-19 C1 ∆VOS (t3) C2 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS φ1 = 1 C1 Vi φ2 = 1 C2 C’2 C1 V C’2 a Vo Va C2 Vo Ao Ao Consider the finite dc gain effect only. Let VOS = 0, and 1 Ao = µ C1 k= C2 j= C2 1 C2 = (1 + k )µ 2 = (1 + j )µ At t = t2 Vo(t2) ≈ Vo(t1) − j (1 − 2 )Vo (t1 ) = 1 − j µ + (1 + j )µ2 Vo(t1) • Note that Va is reset from −µVo (t1) to 0. SC Filters 23-20 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS At t = t3, assuming Vi = 0, then Vo(t3) = Vo(t2) + [µVo (t2) + Va] + kVa = −Ao [Va − µVo(t2)] ⇒ 1 Vo(t3) = 1 + Vo(t2) ≈ 1 + µ − (1 + k )µ2 Vo(t2) 1 + k + Ao Including Vi , we have Vo(t3) ≈ −k (1 − + 1 + µ − (1 + k )µ2 Vo(t2) ≈ −k (1 − SC Filters 1)Vi (t3 ) 1)Vi (t3 ) + 1 + (1 − j )µ − kµ2 Vo(t1) 23-21 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS If j = C2/C2 = 1, the output difference equation becomes Vo(n) = −k (1 + ∆α )Vi (n) + (1 + ∆β )Vo(n − 1) C1 1 · ∆α = −(1 + k )µ = − 1 + C2 Ao ∆β = −kµ2 = − C1 1 · C2 A2 o • Reference: W. Ki, el. al., “Offset-Co...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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