Analog Integrated Circuits (Jieh Tsorng Wu)

Single t gain stages 5 4 analog ics jieh tsorng wu

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Unformatted text preview: g ICs; Jieh-Tsorng Wu Latch-Up in CMOS Technologies VDD Rn Q2 Q1 Rp • Keep Rp and Rn small by having low-impedance paths between the substrate and well to the power supplies. • Avoid currents flowing in substrate and wells. • Transistors that conduct large current must be surrounded by guard rings. Technologies 4-28 Analog ICs; Jieh-Tsorng Wu Single-Transistor Gain Stages Jieh-Tsorng Wu ES A October 25, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Unilateral Two-Port Network Thevenin Output Model i1 v1 Norton Output Model Zo Zi i2 Avv1 v2 v1 Zi = i1 v2 Av = v1 Single-T Gain Stages i2 = 0 i2 i1 v1 v2 Zo = i2 i2 Gm = v1 5-2 v2 =0 Zi Gm v1 Zo v2 v1 =0 Av = Gm × Zo Analog ICs; Jieh-Tsorng Wu Common-Emitter Configuration VCC RL RS IB VO + vo Q1 vi VI • DC voltage VI establishes bias of Q1 so that it is on the forward-active region. Typically want VO ≈ VCC /2. Single-T Gain Stages 5-3 Analog ICs; Jieh-Tsorng Wu Common-Emitter Configuration — Bias Analysis RS VI IC IB VBE RL VCC IC = IS eVBE /UT = βF IB If Q1 is in the forward-active region, voltage across the emitter junction can be approximated by a constant VBE (on) . IB = VI − VBE (on) RS RL VO = VCC − IC RL = VCC − βF IB RL = VCC − βF V − VBE (on) RS I • Dependence on βF is a problem with this direct approach to biasing. Single-T Gain Stages 5-4 Analog ICs; Jieh-Tsorng Wu Common-Emitter Configuration — Small-Signal Analysis rb RS io ii vi v1 vo Av (0) ≡ vi =− ω=0 Ri ≡ rπ rπ RS + rπ vi = RS + rπ ii g m v1 · gm · (ro RL) Ro ≡ vo io vi =0 ro where RL vo RS ≡ RS + rb = ro RL = RL • Note that for RS → 0 and RL → ∞ VA 1 Av (0) → −gmro = − = − η UT Single-T Gain Stages 5-5 Analog ICs; Jieh-Tsorng Wu Common-Source Amplifier VDD Z L vo + V O RS M1 v in + V IN - 1 W Vo = VDD − Id · RL = VDD − µnCox (Vi − Vtn)2 · RL 2 L • DC voltage VI is chosen to bias M1 so that M1 is in active (saturation) region and its drain voltage is near the midpoint of the output swing (VO ≈ VDD /2). Single-T Gain Stages 5-6 Analog ICs; Jieh-Tsorng Wu Common-Source Configuration — Small-Signal Analysis ii v in RS io v gs r o gv m gs v o R L Av (0) = −gm(ro RL) = −gmRL Ri = ∞ Ro = ro RL = RL • Note that for RL → ∞, RL → ro, and |Av (0)|max = gmro = Single-T Gain Stages ID Vov /2 × Lef f ∂ Lef f ID 5-7 ∂VDS −1 = 2Lef f ∂ Lef f Vov −1 ∂VDS Analog ICs; Jieh-Tsorng Wu Common-Emitter Configuration Small-Signal AC Analysis RS Cµ rb io ii vi i1 ⇒ rπ v1 R1 C if v 1 v s Cπ C vs = vi × Single-T Gain Stages RS + rb C1 = Cπ v o 1 R1 = (RS + rb) rπ C2 = CL + Ccs 5-8 vo io f gv m1 (RS + rb) rπ ro g m v1 RL R 2 C 2 R2 = ro RL Cf = Cµ Analog ICs; Jieh-Tsorng Wu Common-Source Configuration Small-Signal AC Analysis C RS v gs v in C gd v o r o gs gv m gs i1 ⇒ R1 v 1 v s C if C Single-T Gain Stages R1 = RS C L v o 1 R2 = ro RL L io f gv m1 vs = vi R C1 = Cgs 5-9 R C 2 C2 = CL 2 Cf = Cgd Analog ICs; Jieh-Tsorng Wu Miller Approximation i1 v s R1 C if v 1 C io f v o 1 gv m1 vo = (−gmv1 + if ) R2 1 sC2 R 2 C 2 if = (v1 − vo)sCf If R2-C2 is a non-dominant pole, then, at the frequencies of interest vo ≈ −gmR2v1 if ≈ (v1 + gmR2v1)sCf ⇒ if = s(1 + gmR2)Cf = sCM vi CM = (1 + gmR2) · Cf = (1 + av 0) · Cf = Miller Capacitance Single-T Gain Stages 5-10 Analog ICs; Jieh-Tsorng Wu Miller Approximation Equivalent Circuit i1 v s R1 io v 1 C v o t gv m1 R 2 C 2 Ct = C1 + CM = C1 + (1 + gmR2)Cf Av (s) = vo 1 = Av (0) vs (1 − s/p1 )(1 − s/p2 ) Av (0) = −gmR2 Single-T Gain Stages 1 p1 = R1Ct 5-11 1 p2 = R2C2 Analog ICs; Jieh-Tsorng Wu Short-Circuit Current Gain C if v 1 ii R 1s C io f 1 gv m1 io ≈ −gm × v1 = −gm × i1 R1s 1 + R1s (C1 + Cf )s β0 gmR1s io Short-Circuit Current Gain = β (s) = − = = ii 1 + R1s (C1 + Cf )s 1 + R1s (C1 + Cf )s gm Transition Frequency = ωT ≈ C1 + Cf ωT 1 1 gm −3 dB Frequency = ωβ = = = β0 R1s (C1 + Cf ) β0 C1 + Cf Single-T Gain Stages 5-12 Analog ICs; Jieh-Tsorng Wu BJT Transition Frequency For BJTs, we have R1s = rπ C1 = Cπ Cf = Cµ gm Cπ + Cµ Cj e Cj c Cπ Cµ Cb Cj e Cj c 1 τT = = + = + + = τF + + ωT gm gm gm gm gm gm gm ωT = 2πfT = Single-T Gain Stages 5-13 Analog ICs; Jieh-Tsorng Wu MOST Transition Frequency For MOSTs, we have R1s = ∞ 2 C1 = Cgs = Cox W L 3 Cf = Cgd gm ωT = 2πfT = Cgs + Cgd To calculate intrinsic device speed, let ωT ≈ gm/Cgs . • For square-law device, W gm = µCox Vov L ⇒ 3µ ωT = · ·V 2 L2 ov • For device with carrier velocity saturation, gm = W Cox vscl Single-T Gain Stages ⇒ 5-14 ωT = 3 vscl · 2L Analog ICs; Jieh-Tsorng Wu MOST Transition Frequency — Weak Inversion For MOSTs in the weak inversion region, gm ωT = Cgb Cox ID gm = UT Cox + Cd epl Cgb = W L × Cox Cd epl Cox + Cd epl It ID 1 1 1 ID ωT = · = · · · 2I UT W LCd epl UT Cd epl L M • IM = It · W/L is the maximum ID for device in weak inversion. Since It ∝ Dn and Dn = µUT , we have ωT Single-T Gain Stages Dn ID · 2I L M 5-15 ID µ · UT · 2 IM L Analog ICs; Jieh-Tsorng Wu Complete AC Analysis of Common-Emitter(Source) Amplifier R1 i1 v 1 v s C if C io f v o 1 gv m1 Av (s) = vo(s) vs (s) = Av (0) R 2 C 2 1 − s/z1 1 + b1s + b2s2 Av (0) z1 = b1 = R1(C1 + Cf ) + R2 (C2 + Cf ) + gmR1R2Cf b2 Single-T Gain Stages = −gmR2 gm + Cf = R1R2(C1 C2 + C1Cf + C2Cf ) 5-16 Analog ICs; Jieh-Tsorng Wu Complete AC Analysis of Common-Emitter(Source) Amplifier Using the dominant-pole appr...
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