Analog Integrated Circuits (Jieh Tsorng Wu)

Stages 5 32 analog ics jieh tsorng wu emitter

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Unformatted text preview: m v1 VO + vo vi VI v1 IBIAS RL CL RL CL vo RS = RS + rb • It is a voltage buffer, i.e., voltage gain 1, high Zi n, and low Zout . • Neglect Cµ, re, rc, and ro in the following analysis. Single-T Gain Stages 5-29 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Voltage Gain Summing currents at the output, we have ii v1 + gmv1 = (GL + sCL )vo ii = (gπ + sCπ )v1 vi = RS ii + v1 + vo We have Av (s) = Av (0) = gm + gπ + sCπ gm + gπ + sCπ + (GL + sCL )[1 + RS (gπ + sCπ )] gm + gπ gm + gπ + GL(1 + RS gπ ) z1 = − b1 = = gm/αo 1 gm/αo + R (1 + gmRS /βo) L gm + gπ Cπ =− gm/αo Cπ RL[Cπ (1 + RS /RL) + CL(1 + gmRS /βo)] 1 + gm(RL /αo + RS /βo) Single-T Gain Stages = Av (0) 5-30 = 1 − s/z1 1 + b1s + b2s2 gmRL gmRL + αo + gm R S βo + 1 −ωT b2 = RLRS Cπ CL 1 + gm(RL /αo + RS /βo) Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Voltage Gain • If CL = 0, then b2 = 0 and Av (s) = Av (0) 1 − s/z1 1 − s/p1 1 + gm(RL/αo + RS /βo) 1 + gmRL p1 = − ≈− (RL + RS )Cπ (RL + RS )Cπ Av (0) & z1 are unchanged from case where CL = 0. • If RS = 0, again b2 = 0 and Av (s) = Av (0) 1 − s/z1 1 − s/p1 1 + gmRL/αo gmRL gmRL gm ≈ p1 = − if gmRL ≈− αo + gmRL 1 + gmRL Cπ + CL RL(Cπ + CL) z1 is unchanged from case where RS = 0. Av (0) = Single-T Gain Stages 5-31 1 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Input Impedance Zi n(s) = vi (s) ii (s) = RS + 1 + gm/(gπ + sCπ ) 1 − s/z1 1 + = RS + Ri n gπ + sCπ GL + sCL 1 − s/p1 1 − s/p2 Ri n = (GL + gm/αo)/(GL + gπ ) = rπ + (βo + 1)RL ≈ rπ (1 + gmRL) z1 = − gm/αo + GL (βo + 1)Cπ + CL =− 1 + gmRL/αo RL[(βo + 1)Cπ + CL] gm ωT 1 =− − p1 = − rπ Cπ βoCπ βo ≈− (βo + 1)Cπ + CL 1 p2 = − RLCL B If CL = 0, then Zi n(s) = RS + Zi n 1 + gmRL + RL gπ + sCπ gm if gmRL 1 B’ RS (1 + gmRL)rπ Cπ /(1 + gmRL) RL Single-T Gain Stages 5-32 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Output Impedance The output impedance looking into the transistor’s emitter is Zout (s) = Zout (0) = Rout = 1 + RS (gπ + sCπ ) gm + gπ + sCπ 1 + RS gπ = rπ + RS = Rout = 1 − s/z1 1 − s/p1 rπ + RS Zout (∞) = RS gm + gπ gmrπ + 1 βo + 1 1 + RS gπ rπ + RS gm/αo 1 z1 = − =− =− p1 = − Cπ RS Cπ rπ RS Cπ (rπ RS )Cπ • If rπ RS > αo/gm (or RS > 1/gm if βo behavior. • In addition, if RS rπ |z1| ≈ Single-T Gain Stages −ωT 1), |z1| < |p1 |, which represents inductive gm |p1 | 1 = ≈ rπ Cπ βoCπ βo 5-33 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Output Impedance If βo 1, Zout (s) can be rewritten as: Zout (s) = rπ + RS + sCπ rπ RS βo + 1 + sCπ rπ If R2 Single-T Gain Stages RS βo R + sCπ rπ βS RS o RS RS + sCπ rπ β o (R1 + sL)R2 (R1 + sL)R2 ≈ Zout (s) = R1 + R2 + sL R2 + sL R1 L + R1, we have Zout R2 ≈ 1 gm Then RS 1 + R1 = g m βo 5-34 R2 = RS L = Cπ rπ RS βo Analog ICs; Jieh-Tsorng Wu Common-Drain Configuration (Source Follower) C vg VDD Vg v gs1 I in M1 Vo I in R R S g gd1 C I Bias S M2 C S C C S g v m1 gs1 gs1 g o2 C’ L Simplified Small-Signal Model ig vg v gs1 I in Yg R Single-T Gain Stages g o1 v o L Bias CS = CS + Cgd 1 v mb1 o S C’ S CL = CL + Csb1 + Cd b2 + Cgd 2 5-35 C v g m1 gs1 v o gs1 R’ L C’ GL = go1 + go2 + gmb1 = L 1 RL Analog ICs; Jieh-Tsorng Wu Source Follower’s Gate Voltage Gain Summing the currents at the output node, we have (gm1 + sCgs1 )(vg − vo) − vo(sCL + GL) = 0 The voltage gain from gate to output is Avg (s) ≡ vo(s) vg (s) = gm1 + sCgs1 gm1 + GL + s(Cgs1 + CL) gm1 gm1 Avg (0) = = gm1 + GL gm1 + gmb1 + go1 + go2 gm1 z1 = − ≈ −ωT Cgs1 Single-T Gain Stages 5-36 p1 = − = Avg (0) 1 − s/z1 1 − s/p1 Avg (∞) = Cgs1 Cgs1 + CL gm1 + GL Cgs1 + CL Analog ICs; Jieh-Tsorng Wu Source Follower’s Gate Voltage Gain A vg For most practical cases 1 |p1| > |z1| go1 + go2 gm1 + gmb1 = gm1(1 + χ ) A vg (0) (C ’ = 0) L ω p1 p1 ≈ gm1 gm1 + gmb1 ≈ Avg (0) 1 1 + χ1 ≈ − ≈ A vg |p1| = |z1| A vg (0) ω gm1(1 + χ1) Cgs1 + CL (1 + χ1) 1 CL 1+C A vg z1 |p1| < |z1| A vg (0) ω gs1 p1 Single-T Gain Stages 5-37 z1 Analog ICs; Jieh-Tsorng Wu Source Follower’s Gate Input Impedance The input admittance looking into the gate is Yg (s) = ig vg = sCgs1 [1 − Avg (s)] = sCgs1 (GL + sCL) gm1 + GL + s(Cgs1 + CL) Define the capacitance looking into the gate as Yg (s) = sCg (s) Cg (j ω) = Cgs1 [1 − Avg (j ω)] Cg (0) = Cg Cgs1 [1 − Avg (0)] Cg (∞) = Cgs1 [1 − Avg (∞)] = Cg (∞) Cgs1 CL Cgs1 + CL Cg (0) ω |p1| Single-T Gain Stages 5-38 |z1| Analog ICs; Jieh-Tsorng Wu Source Follower’s Output Impedance g ig vg m1 < 1 R |Zo| S 1/g C R v gs1 gs1 S v g m1 gs1 m1 R v o ω S 1 io Equivalent Circuit C g m1 > Zo 1 R S 1/g L S Rs m1 ω g 1 C io = −(gm1 + sCgs1 )(vg − vo) Single-T Gain Stages R |Zo| R2 R1 gs1 5-39 gs1 R S C m1 gs1 GS vg + sCgs1 (vg − vo) = 0 Analog ICs; Jieh-Tsorng Wu Source Follower’s Output Impedance The output admittance is GS (gm1 + sCgs1 ) GS (gm1 − GS ) io 1 = = GS + = GS + ≡ Yo(s) = GS + sCgs1 GS + sCgs1 Zo(s) vo • Note that Zo(0) = 1 gm1 1 1 g m1 − G S + sCgs1 RS g m1 − G S Zo(∞) = RS • The equivalent circuit is 1 R1 = gm1 − GS Single-T Gain Stages R2 = RS 5-40 L= RS Cgs1 gm1 − GS Analog...
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