Analog Integrated Circuits (Jieh Tsorng Wu)

State a is stable and desirable state b where only

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Unformatted text preview: Sources VCC VDD R R VC2 VD2 IC2 Q1 ID2 Q2 IC2 ≈ IC1 ≈ M1 VCC − VBE 1(on) R ≈ VCC ∂IC2 VCC VCC ∂ = · = · IC2 ∂VCC VCC /R ∂VCC R ∂IC2 1 ∂VCC VCC ∂R 1 ∂VCC 1 ∂R = − = IC2 − 2 ∂T ∂T R ∂T VCC ∂T R ∂T R I SVC2 CC Voltage and Current References 9-3 M2 VCC R =R· ⇒ 1 R =1 TCIC2 = TCVCC − TCR Analog ICs; Jieh-Tsorng Wu BJT Widlar Current Source Let βF → ∞ and VA → ∞, VCC R1 IIN Q1 IIN ≈ IO VCC − VBE 1 R1 ≈ VCC I SVIN ≈ 1 R1 CC IO IIN IIN IS 2 UT ln = UT ln + IO R2 ⇒ UT ln · IS 1 IS 2 IO IS 1 Q2 R2 If IS 1 = IS 2 ⇒ = IO R2 IIN UT ln = IO R2 IO Differentiating both sides of the above equation with respect to VCC , UT IO IIN IO SV CC ∂IO I ∂I ∂IO IIN ∂IO 1 ∂IIN 1 O IN = R2 − ⇒ = IR IO ∂VCC I 2 ∂VCC ∂VCC ∂VCC 1 + O 2 IIN ∂VCC O UT VCC ∂IO V ∂I 1 1 1 CC IN = S IIN ≈ = = VCC IO R 2 IO R 2 IR IO ∂VCC IIN ∂VCC 1+ U 1+ U 1+ O 2 U T Voltage and Current References T 9-4 T Analog ICs; Jieh-Tsorng Wu MOST Widlar Current Source Let VA → ∞ and γ → 0, VDD IIN R1 IO M1 VDD − Vov 1 − Vt IIN = M2 1 =k 2 R1 Vov 1 = Vov 2 + IO R2 ⇒ W L 1 IO R2 + R2 IO = 1 ∂IO 2 IO ∂VDD 1 = 4R2 I SVO DD 1 2R2 1 2 k (W/L)2 + 4R2Vov 1 4R2 Vov 1 = 2 Vov 2 + 4IOR2Vov 1 Voltage and Current References 2 − k (W/L)2 ∂Vov 1 ∂VDD ∂VDD I SVIN DD 9-5 ≈ Vov 1 2 4Vov 1 2IO k (W/L)2 2 + ∂Vov 1 Vov 1 = 2 Vov 1 k (W/L)2 = 2IIN k (W/L)1 − Vov 1 = 0 + 4R2Vov 1 ∂IIN k (W/L)1 2 IIN ∂VDD 2 1 1I I SVIN = SVIN DD 2 DD Analog ICs; Jieh-Tsorng Wu BJT Peaking Current Source VCC Since IIN VBE 1 − IIN R = VBE 2 R IO IIN UT ln − IIN R = UT ln IS 1 IS 2 IO Q1 Q2 We have UT ln IIN IS 2 · IO IS 1 = IIN R If Q1=Q2, then IO = IIN e−IIN R/UT Voltage and Current References 9-6 R= UT IIN ln IIN IO Analog ICs; Jieh-Tsorng Wu MOST Peaking Current Source VDD For M1 and M2 in strong inversion IIN 1 IO = k 2 W L 1 2 Vov 2 = k 2 2 R IO M1 Vov 1 = W L (Vo1 − IIN R )2 2 2IIN k (W/L)1 M2 For M1 and M2 in weak inversion region, VGS 2 − Vt = nUT ln IIN (W/L)1 It − IIN R If M1=M2, IO ≈ It Voltage and Current References 9-7 W L e(VGS 2−Vt )/(nUT ) ≈ IIN e−IIN R/(nUT ) 2 Analog ICs; Jieh-Tsorng Wu BJT VBE Referenced Current Source VCC IO R1 IIN IIN = Q2 VCC − VBE 1 − VBE 2 VBE 1 Q1 ∂VCC I SVO CC = UT IS 1 = R2 IIN VCC ∂ IO IO ∂VCC Voltage and Current References = IIN = UT ln IS 1 IO = VBE 1 UT IIN = ln R2 R2 IS 1 IIN ∂IS 1 1 ∂IIN − IS 1 ∂VCC I 2 ∂VCC S1 UT 1 ∂IIN = R2 IIN ∂VCC R2 ∂IO R1 VCC IO UT IIN UT UT 1 ∂IIN I = SV = SVIN R2 IIN ∂VCC IO R2 CC VBE 1(on) CC 9-8 Analog ICs; Jieh-Tsorng Wu MOST Vt Referenced Current Source VDD IIN R1 IO IIN = M2 VDD − VGS 1 − VGS 2 R1 VDD − Vov 1 − Vov 2 − Vt1 − Vt2 R1 2IIN Vov 1 = M1 = Vov 2 = k (W/L)1 R2 IO = I SVO DD Voltage and Current References = Vov 1 2IO R2 VGS 1 R2 I SVIN DD 9-9 = = Vt1 + Vov 1 R2 Vov 1 2VGS 1 Vt1 + = 2IO k (W/L)2 2IIN k (W/L)1 R2 I SVIN DD Analog ICs; Jieh-Tsorng Wu Self-Biasing BJT VBE Reference VCC Q4 Q3 IO Q6 IO1 IO IIN IIN ≈ IO · Q2 IS 4 VBE 1 UT IIN = ln IO ≈ R R IS 1 A IO2 IS 3 Q5 Q1 IIN R B TCIO = TCVBE 1 − TCR VEE • Two possible operating states, A and B. State A is stable and desirable. • State B, where only leakage currents flow, would normally be unstable. However, it may become stable due to low loop gain under low-current condition. • There may exist hidden states when the supply is ramping from 0 V. Voltage and Current References 9-10 Analog ICs; Jieh-Tsorng Wu Self-Biasing BJT VBE Reference with Start-Up Circuit VCC Q4 Q3 Q6 Rs D5 IIN 4V BE(on) D4 IO1 Rx IO • Choose Rx so that, in State A, Vx Q2 Q5 Q1 D1 Vx = IIN Rx ≥ 2VBE (on) IO2 D3 D2 • When in zero-current state (B), Vx ≈ 0, and D5 is forward biased, forcing a current flowing into the self-basing loop. R Thus, D 5 is reversed biased and the startup circuit won’t disturb the self-biasing loop when in State A. VEE • The start-up circuit may also introduce additional bias points. Voltage and Current References 9-11 Analog ICs; Jieh-Tsorng Wu Self-Biasing BJT UT Reference VCC Q4 IO Q6 Q3 IIN ≈ IO · IO2 I IN Q2 Q1 A R Q5 V BE IS 4 IO IIN UT ln = UT ln + IO R IS 1 IS 2 IO IO1 IS 3 I IN TCIO = TCUT − TCR B VEE ∆VBE = VBE 1 − VBE 2 = UT ln IIN IS 2 · IO IS 1 = UT ln IS 3 IS 2 · IS 4 IS 1 IO = ∆VBE R • The UT reference is a proportional-to-absolute-temperature (PTAT) circuit. • A start-up circuit is required to avoid the “zero-current” state. Voltage and Current References 9-12 Analog ICs; Jieh-Tsorng Wu Self-Biasing MOST Vt Referenced Current Source VDD M12 M4 M3 M6 IO1 IIN M2 M13 M11 Vov 1 = IO IO2 Vov 2 = M5 M1 R 2IIN k (W/L)1 2IO k (W/L)2 Start-Up IIN (W/L)3 = IO (W/L)4 Voltage and Current References IO = VGS 1 R = Vt1 + Vov 1 9-13 R Vt1 + = 2IIN k (W/L)1 R ≈ Vt1 R Analog ICs; Jieh-Tsorng Wu Self-Biasing MOST gm Referenced Current Source VDD VDD M4 M3 M6 M4 M3 IO1 IIN IO M2 M1 IO1 IIN IO2 IO V α≡ (W/L)2 (W/L)1 >1 R M5 R k = µn Cox ∆V = I · R...
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