Analog Integrated Circuits (Jieh Tsorng Wu)

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Unformatted text preview: (INL) improves with ADCs √ m. 25-65 Analog ICs; Jieh-Tsorng Wu Bending at the Edges Due to Averaging Input and Reference R-String Averaging R-String Do Vi Use Resistor-Ring to Mitigate Edge Effect ADCs 25-66 Analog ICs; Jieh-Tsorng Wu Cascaded Folding Input and Reference R-String Averaging Resistor Ring and 3X Folding Averaging Resistor Ring and 3X Folding Dc Vi M-ADC • Too many folding in one stage can cause gain-loss. • Require odd number of single-stage folding to maintain continuity. ADCs 25-67 Analog ICs; Jieh-Tsorng Wu Differential Preamplifier VDD M3 M5 M6 M4 Ad m = gm1 · Vo M1 Acm = M2 Vi VBN 1 gm3 − gm5 gm1 1 · 1 + 2gm1ro7 gm3 + gm5 M7 VSS • Additional common-mode feedback is not required. ADCs 25-68 Analog ICs; Jieh-Tsorng Wu A CMOS 10-Bit Folding ADC — Bult • Reference: K. Bult, et. all, “An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 2 1-mm ,” JSSC 12/1997, pp. 1887–1895. ADCs 25-69 Analog ICs; Jieh-Tsorng Wu Time-Interleaved Architectures Ai Tc φ1 S/H φ2 S/H φm S/H φ1 φ2 ADC 1 ADC m N Do ADC 2 N N φm N t Multiplexer • The equivalent sampling rate is m/Tc. • Clock phase as well as clock jitter need to satisfy N-bit accuracy. • Any mismatch among the converter characteristics, including offset and gain, can appear as noises and/or spurious tones in Do. ADCs 25-70 Analog ICs; Jieh-Tsorng Wu Oversampling Converters Jieh-Tsorng Wu ES A July 16, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Sampling and Quantization pdf of e(k) Quantizer x(k) x(t) D(z) y(k) e(k) fs /2 N−Bit /2 | D(f) | e(k) S e (f) x(k) D(z) y(k) f f s /2 f 0 B f B f s /2 e(k ) is a quantization noise due to the quantization process. With an ideal quantizer with step size ∆, The pdf of e(k ) is assumed to be uniformly distributed over −∆/2 and +∆/2. e(k ) ≡ y (k ) − x (k ) Oversampling Noise Power = Pn = 26-2 e2pdf(e)d e = 12 ∆ 12 Analog ICs; Jieh-Tsorng Wu Oversampling Assume the noise e(k ) is white and is independent of fs , then the noise spectral density is Pn 121 ∆× = Sn(f ) = 12 fs fs For a full-scale sinusoidal input 1 x (k ) = A sin(2πfi · kTs ) 2 A = 2N ∆ Signal Power = Ps = 1 2 1 2N 2 ·A = ·2 ∆ 8 8 Assume the bandwidth of x (k ) is limited to fB . The oversampling ratio, OSR, is defined as fs OSR = 2fB The noise at the output of D (z ) filter is Pn = Oversampling + fB − fB 1 2 2fB ∆× Sn(f ) · d f = 12 fs 26-3 Analog ICs; Jieh-Tsorng Wu Oversampling The signal-to-noise ratio of y (k ) becomes SNRy,max Ps fs 3 2N ≡ = ×2 × = 1.76 + 6.02 · N + 10 log(OSR) dB 2fB Pn 2 • Oversampling gives a SNR improvement of 3 dB/octave or 0.5 bit/octave. • High-speed digital filters, D (z ), are required. • Oversampling also eases the anti-alias filter design for x (t ). • Oversampling does not improve linearity. Linear quantizers are still required. • One-bit quantizers and one-bit DACs are inherently linear. Therefore, they are often used in oversampling converters. Oversampling 26-4 Analog ICs; Jieh-Tsorng Wu First-Order ∆Σ Modulator e(k) y(k) x(t) Integrator x(k) z 1 u(k) y(k) D/A Y (z ) = z −1 X (z ) Y (z ) Noise Transfer Function = NT F (z ) = = 1 − z −1 E (z ) Signal Transfer Function = ST F (z ) = The noise transfer function in frequency domain is NT F (f ) = NT F (z )|z=ej 2πf /fs = sin πf fs × 2j × e−j πf /fs • Noise power is small near f = 0 and becomes large near f = fs /2. Oversampling 26-5 Analog ICs; Jieh-Tsorng Wu First-Order ∆Σ Modulator The quantization noise power in the fB frequency band is Pn = If OSR + fB − fB Se(f )|NT F (f )|2d f = + fB − fB 2 ∆1 πf 2 sin 12 fs fs 2 · df 1, then 2 2 ∆π · Pn ≈ 12 3 SNRy,max ≡ Ps Pn = 2fB fs 3 22 ∆π 1 = 36 OSR3 9 × 22N × OSR3 = −3.41 + 6.02 · N + 30 log(OSR) dB 2π2 • Oversampling gives a SNR improvement of 9 dB/octave or 1.5 bit/octave. • The integrator’s output is u(k + 1) = x (k ) − e(k ). If x is a dc input and bounded by the full range of D/A, then |e| < ∆/2 and |u|max = |x | + ∆/2. Oversampling 26-6 Analog ICs; Jieh-Tsorng Wu First-Order ∆Σ Modulator with SC Circuit Implementation Vi C1 1 2 CA 2 y(n) 1 2 VR 2, 1 C2 1, 2 • One-bit ∆Σ modulator. VR = ∆/2. • The comparator latches on the falling edge of φ2. The output y (n) ∈ {+1, −1}. • C1 and C2 can be combined into one capacitor. Oversampling 26-7 Analog ICs; Jieh-Tsorng Wu Circuit Considerations For an ideal integrator H (z ), we have −1 H (z ) ST F (z ) = = z −1 1 + H (z ) z H (z ) = 1 − z −1 1 NT F (z ) = = 1 − z −1 1 + H (z ) • If the integrator includes a gain factor G , then −1 z H (z ) = G × 1 − z −1 −1 Gz ST F (z ) = 1 − (1 − G )z−1 −1 1−z NT F (z ) = 1 − (1 − G )z−1 – Small deviations of G from unity have little effect on the overall performance, provided the net gain in the feedback loop is large. – 10% gain accuracy of G is tolerable. Oversampling 26-8 Analog ICs; Jieh-Tsorng Wu Circuit Considerations • If the opamp has a finite gain of Ao, then −1 z H (z ) ≈ 1 − βz −1 where β =1− 1 Ao −1 z −1 ST F (z ) = 1 + (1 − β )z−1 1 − βz NT F (z ) = 1 + (1 − β )z−1 – NT F (f ) is flat for 2πf /fs < 1/Ao. fs /(2πAo) or Ao OSR/π. – Want fB – Usually want Ao > 2OSR. • Noises or harmonics arising from the quantizer’s nonlinearity are suppressed by NT F (z ), making the quantizer less critical. • The linearity of the D/A...
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