Unformatted text preview: (INL) improves with
ADCs √
m. 2565 Analog ICs; JiehTsorng Wu Bending at the Edges Due to Averaging
Input and Reference RString Averaging RString
Do Vi
Use ResistorRing to Mitigate Edge Effect ADCs 2566 Analog ICs; JiehTsorng Wu Cascaded Folding
Input and Reference RString Averaging Resistor Ring and 3X Folding Averaging Resistor Ring and 3X Folding Dc
Vi
MADC • Too many folding in one stage can cause gainloss.
• Require odd number of singlestage folding to maintain continuity.
ADCs 2567 Analog ICs; JiehTsorng Wu Diﬀerential Preampliﬁer
VDD M3 M5 M6 M4 Ad m = gm1 · Vo
M1 Acm = M2 Vi
VBN 1
gm3 − gm5 gm1
1
·
1 + 2gm1ro7 gm3 + gm5 M7
VSS • Additional commonmode feedback is not required. ADCs 2568 Analog ICs; JiehTsorng Wu A CMOS 10Bit Folding ADC — Bult • Reference: K. Bult, et. all, “An Embedded 240mW 10b 50MS/s CMOS ADC in
2
1mm ,” JSSC 12/1997, pp. 1887–1895.
ADCs 2569 Analog ICs; JiehTsorng Wu TimeInterleaved Architectures
Ai Tc φ1 S/H φ2 S/H φm S/H φ1
φ2 ADC
1 ADC
m N
Do ADC
2
N N φm N t Multiplexer • The equivalent sampling rate is m/Tc.
• Clock phase as well as clock jitter need to satisfy Nbit accuracy.
• Any mismatch among the converter characteristics, including oﬀset and gain, can
appear as noises and/or spurious tones in Do. ADCs 2570 Analog ICs; JiehTsorng Wu Oversampling Converters JiehTsorng Wu ES A July 16, 2002 1896 National ChiaoTung University
Department of Electronics Engineering Sampling and Quantization
pdf of e(k)
Quantizer
x(k) x(t) D(z) y(k) e(k) fs /2 N−Bit /2
 D(f)  e(k)
S e (f)
x(k) D(z) y(k) f
f s /2 f 0
B f B f s /2 e(k ) is a quantization noise due to the quantization process. With an ideal quantizer with
step size ∆, The pdf of e(k ) is assumed to be uniformly distributed over −∆/2 and +∆/2.
e(k ) ≡ y (k ) − x (k ) Oversampling Noise Power = Pn = 262 e2pdf(e)d e = 12
∆
12 Analog ICs; JiehTsorng Wu Oversampling
Assume the noise e(k ) is white and is independent of fs , then the noise spectral density
is
Pn
121
∆×
=
Sn(f ) =
12
fs
fs
For a fullscale sinusoidal input
1
x (k ) = A sin(2πfi · kTs )
2 A = 2N ∆ Signal Power = Ps = 1 2 1 2N 2
·A = ·2 ∆
8
8 Assume the bandwidth of x (k ) is limited to fB . The oversampling ratio, OSR, is deﬁned
as
fs
OSR =
2fB
The noise at the output of D (z ) ﬁlter is
Pn = Oversampling + fB
− fB 1 2 2fB
∆×
Sn(f ) · d f =
12
fs 263 Analog ICs; JiehTsorng Wu Oversampling
The signaltonoise ratio of y (k ) becomes
SNRy,max Ps fs
3
2N
≡
= ×2 ×
= 1.76 + 6.02 · N + 10 log(OSR) dB
2fB
Pn 2 • Oversampling gives a SNR improvement of 3 dB/octave or 0.5 bit/octave.
• Highspeed digital ﬁlters, D (z ), are required.
• Oversampling also eases the antialias ﬁlter design for x (t ).
• Oversampling does not improve linearity. Linear quantizers are still required.
• Onebit quantizers and onebit DACs are inherently linear. Therefore, they are often
used in oversampling converters. Oversampling 264 Analog ICs; JiehTsorng Wu FirstOrder ∆Σ Modulator
e(k)
y(k)
x(t) Integrator x(k) z 1 u(k) y(k) D/A Y (z )
= z −1
X (z )
Y (z )
Noise Transfer Function = NT F (z ) =
= 1 − z −1
E (z )
Signal Transfer Function = ST F (z ) = The noise transfer function in frequency domain is
NT F (f ) = NT F (z )z=ej 2πf /fs = sin πf
fs × 2j × e−j πf /fs • Noise power is small near f = 0 and becomes large near f = fs /2.
Oversampling 265 Analog ICs; JiehTsorng Wu FirstOrder ∆Σ Modulator
The quantization noise power in the fB frequency band is
Pn =
If OSR + fB
− fB Se(f )NT F (f )2d f = + fB
− fB 2 ∆1
πf
2 sin
12 fs
fs 2 · df 1, then
2 2 ∆π
·
Pn ≈
12 3
SNRy,max ≡ Ps
Pn = 2fB
fs 3 22 ∆π
1
=
36 OSR3 9
× 22N × OSR3 = −3.41 + 6.02 · N + 30 log(OSR) dB
2π2 • Oversampling gives a SNR improvement of 9 dB/octave or 1.5 bit/octave.
• The integrator’s output is u(k + 1) = x (k ) − e(k ). If x is a dc input and bounded by the
full range of D/A, then e < ∆/2 and umax = x  + ∆/2.
Oversampling 266 Analog ICs; JiehTsorng Wu FirstOrder ∆Σ Modulator with SC Circuit Implementation Vi C1 1
2 CA 2 y(n) 1
2 VR 2, 1 C2 1, 2 • Onebit ∆Σ modulator. VR = ∆/2.
• The comparator latches on the falling edge of φ2. The output y (n) ∈ {+1, −1}.
• C1 and C2 can be combined into one capacitor.
Oversampling 267 Analog ICs; JiehTsorng Wu Circuit Considerations
For an ideal integrator H (z ), we have
−1 H (z )
ST F (z ) =
= z −1
1 + H (z ) z
H (z ) =
1 − z −1 1
NT F (z ) =
= 1 − z −1
1 + H (z ) • If the integrator includes a gain factor G , then
−1 z
H (z ) = G ×
1 − z −1 −1 Gz
ST F (z ) =
1 − (1 − G )z−1 −1 1−z
NT F (z ) =
1 − (1 − G )z−1 – Small deviations of G from unity have little eﬀect on the overall performance,
provided the net gain in the feedback loop is large.
– 10% gain accuracy of G is tolerable. Oversampling 268 Analog ICs; JiehTsorng Wu Circuit Considerations
• If the opamp has a ﬁnite gain of Ao, then
−1 z
H (z ) ≈
1 − βz −1 where β =1− 1
Ao
−1 z −1
ST F (z ) =
1 + (1 − β )z−1 1 − βz
NT F (z ) =
1 + (1 − β )z−1 – NT F (f ) is ﬂat for 2πf /fs < 1/Ao.
fs /(2πAo) or Ao
OSR/π.
– Want fB
– Usually want Ao > 2OSR.
• Noises or harmonics arising from the quantizer’s nonlinearity are suppressed by
NT F (z ), making the quantizer less critical.
• The linearity of the D/A...
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 Winter '09
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 Integrated Circuit, Transistor, The Land, Bipolar junction transistor, VDS, Analog ICs, JiehTsorng Wu

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