Analog Integrated Circuits (Jieh Tsorng Wu)

The folding circuit need only to be accurate near the

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Unformatted text preview: −1, 0, +1 Vj+1 A j+1 Vr x D j 1 0.5 Vr Cf Vj+1 g C L C 0.25 Vr 0 Aj 0 0.25 Vr 1 0.5 Vr ADC Dj Minimal+1 ADCs 0 DAC 0.75 Vr 0.25 Vr 0.25 Vr 25-39 0.75 Vr Analog ICs; Jieh-Tsorng Wu A Radix-2 1.5 Bit SC Pipeline Stage During phase 2 g Vj +1 g C C = Vj + (Vj − Vr × Dj ) = 1 + f C Cf Vr = 2 × Vj − × Dj 2 if Vj − Vr 1+ Cf /Cg × Dj Cf = Cg • The full range of the input/output is ±0.5Vr . • The pipeline stage has input over-range capability of ±0.25Vr . ADCs 25-40 Analog ICs; Jieh-Tsorng Wu Multi-Bit Switched-Capacitor Pipeline Stage 2 1 Cf 1 Vj Vj+1 1 Comparator Bank C 2 0 Vr x D j 1 C 0 1 K Dj = Dj · 20 + Dj · 21 + · · · Dj · 2K −1 f g0 g1 2 1 Vr x D j Dj g0 k Dj ∈ {−1, 0, +1} g(K −1) g1 C C C C = = = ··· = =C 20 20 21 2N − 1 Vj +1 = Gj × Vj − ∆V × Dj ADCs Gj = 1 + C g0 +C 25-41 g1 + ··· + C Cf g(K −1) = 2K ∆V = Vr 2K Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Pipelined ADCs The SC stage has a voltage gain of g C G =1+ Cf C g = C g0 + C g1 + C g2 + · · · The settling time requirement can be expressed as f C +C Ts = Gm L g i C C 1+ + f C Cf · ln 2y +1 f ⇒ C +C Gm = Ts L i C G+ Cf · (y + 1) ln 2 Other constraints are Total Power ∝ Gm,1 + Gm,2 + · · · + Gm,P Total Input Referred Thermal Noise Power = Pθ ∼ kT ADCs 25-42 1 1 1 + + ··· s 2Cs 2Cs C1 (G1) 2 (G1 G2) 3 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Pipelined ADCs • Gm is the opamp’s transconductance. i • C is the opamp’s input capacitance. s f g • Cj = Cj + Cj is the j -stage sampling capacitances. s • CL includes Cj +1 and input loading of the comparator bank in the j + 1 stage. • y (bits) is the resolution requirement of the j stage. s s • Use capacitor scaling, α = Cj /Cj +1, total power dissipation can be minimized while maintaining noise performance. It can be shown that αopt ∼ G . • Increasing G (and M ) per stage generally reduces total power dissipation. • Reference: D. Cline and P. Gray, “A Power Optimized 13-b 5Ms/s Pipelined ADC,” JSSC, March 1996, pp. 294–303. ADCs 25-43 Analog ICs; Jieh-Tsorng Wu Single-Stage Calibration and Digital Correction Aj Aj+1 0 1 Ac CAL Gj ADC 0 1 DAC da Aj ADC Z Dz Dj Dc CAL The signal Aj +1 is quantized the following Z-ADC with G ˆ ˆ Aj +1 = Gj · Aj − Ada(Dj ) Aos = · Dz + Qos + Q j j ˆ G os ˆ • G/G is the gain error, Q is the offset, and Q is the quantization error. ADCs 25-44 Analog ICs; Jieh-Tsorng Wu Single-Stage Calibration and Digital Correction ˆda During calibration, Aj is disabled and Aj (Dc) is quantized by measuring ˆ j · Ac − Aos = G · Dz1 + Qos + Q1 G ˆ G G ˆ ˆ Gj · Ac − Ada(Dc) − Aos = · Dz2 + Qos + Q2 j ˆ G Subtracting the above two equations, we have G G ˆˆ Gj · Ada(Dc) = · (Dz1 − Dz2) + Q1 − Q2 = · Dz (Dc) + 2Qc(Dc) j ˆ ˆ G G ⇒ ADCs ˆ Ada(Dc) = j Gj G ˆˆ Gj G c · Tj (Dc) + 2Q (Dc) ˆ Gj 25-45 Dz (Dc) Tj (Dc) = Gj Dc ∈ {Dj } Dc ∈ {Dj } Analog ICs; Jieh-Tsorng Wu Single-Stage Calibration and Digital Correction The combined ADC with j-Stage and Z-ADC has the following characteristic: Aj = ˆ Ada(Dj ) j + Aos j + Aj +1 ˆ Gj Gj G = Dz + = T (D ) + Gj ˆjG j j ˆ G = Gj G ˆˆ Gj G · Tj (Dj ) + Qos Aos + j ˆ Gj 2Qc(Dj ) ˆ Gj + Aos j + Aj +1 ˆ Gj c + 2Q (Dj ) + Q ˆ Gj G · Dz + Q os + Q ˆ G Dz Digital Output = Dz = Tj (Dj ) + Gj Gj G G Gain Error = = ˆ ˆˆ G Gj G c os Offset = Q os Q os = Aj + ˆ Gj Quantization Error = Q = 2Q (Dj ) ˆ Gj Q + ˆ Gj ˆda ˆ • Nonideal Aj and Gj have no effect on the A/D linearity. ADCs 25-46 Analog ICs; Jieh-Tsorng Wu Multi-Stage Calibration and Digital Correction A i Stage 1 A2 Stage 2 Stage P-1 D2 D1 Table DP-1 Table T1 AP DP TP-1 Qx Table TP d GP-1 d G1 Stage X Dx Table Table T2 AP+1 Stage P Tx d GP Do Assume the stage X ADC has a characteristic of AP +1 = Gx ˆ Gx os · Tx + Qx + Qx • Calibration is performed stage-by-stage, from Stage P to Stage 1. ADCs 25-47 Analog ICs; Jieh-Tsorng Wu Multi-Stage Calibration and Digital Correction Use the X ADC to calibrate stage P . Then, the P + X ADC can be expressed as AP = GP Gx ˆˆ GP Gx c os Tx TP + GP + Aos + P Qx + ˆ GP 2Qx,P + Qx ˆ GP Use the P + X ADC to calibrate stage (P − 1). Then, the (P − 1) + P + X ADC can be expressed as AP −1 = GP − 1 GP Gx ˆ ˆˆ GP − 1 GP Gx TP Tx TP −1 + + GP − 1 GP − 1 GP os + Aos 1 + P− AP ˆ GP − 1 c os + Qx ˆ ˆ GP − 1 GP + c 2Qx,P −1 + 2Qx,P + Qx ˆ ˆ GP − 1 GP Repeat the calibration procedures for stage (P − 2), (P − 3), . . . , 2, and 1. ADCs 25-48 Analog ICs; Jieh-Tsorng Wu Multi-Stage Calibration and Digital Correction The full calibrated ADC can be expressed as Ai = GT ˆ GT T2 TP Tx T1 + + ··· + + G1 G1 G2 · · · GP − 1 G1 G2 · · · GP os + QT + QT where GT ˆ GT = G1 G2 · · · GP Gx ˆˆ ˆˆ G1 G2 · · · GP Gx os os os QT = Aos + 1 c QT = ADCs A2 ˆ G1 + ··· + os AP ˆ ˆˆ G1 G2 · · · GP − 1 c c 2Qx,1 + 2Qx,2 + · · · + 2Qx,P + Qx ˆ ˆˆ G1 G2 · · · GP 25-49 ≤ + Qx ˆ ˆˆ G1 G2 + · · · GP (2P + 1) × |Qx |max ˆ ˆˆ G1 G2 · · · GP Analog ICs; Jieh-Tsorng Wu Multi-Stage Calibration and Digital Correction os ˆ • The scaling factor GT /GT and offset QT can be determined by quantizing two known input, e....
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