Analog Integrated Circuits (Jieh Tsorng Wu)

Thus vsb m 1 0 and avg 0 gm1 gm1 go1 go2 the

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Unformatted text preview: ICs; Jieh-Tsorng Wu Source Follower’s Complete Frequency Response A(s) = vo ii n = Avg (s) GS + sCS + Yg = where A(0) = RS · gm1 gm1 + GL = RS · gm1 + sCgs1 b0 + b1s + b2s2 gm1RL 1 + gm1RL = A(0) z1 = − 1 − s/z1 1 + ωsQ + o gm1 Cgs1 s2 ω2 o −ωT b0 = GS (gm1 + GL) b1 = GS (Cgs1 + CL) + (gm1 + GL)CS + GLCgs1 b2 = Cgs1 CL + CS (Cgs1 + CL) and ωo = Q= Single-T Gain Stages GS (gm1 + GL) Cgs1 CL + CS (Cgs1 + CL) GS (gm1 + GL)[Cgs1 CL + CS (Cgs1 + CL)] GS CL + (gm1 + GL)CS + GLCgs1 5-41 Analog ICs; Jieh-Tsorng Wu Source Follower’s Complete Frequency Response • ωo is the pole frequency and Q is the Q-factor. • The bandwidth can be estimated by BW ≈ ωo ≈ gm1 + GL 1 × RS (CS + Cgs1) CL if CL CS √ • If Q < 1/ 2 ≈ 0.707, no peaking in |A(j ω)|. • If Q > 0.5, the poles are complex, and overshoot appears in the step response. √ −π/ 4Q2 −1 % Overshoot = 100e • If gm1 1 ≈ Q GL and CL CS GS CL gm1(Cgs1 + CS ) Single-T Gain Stages + gm1CS GS CL(Cgs1 /CS + 1) 5-42 + GLCgs1 GS (gm1/GL)(1 + CS /Cgs1) Analog ICs; Jieh-Tsorng Wu Compensated Source Follower Yg Vg Yg VDD M1 I in Vo C1 R in C in R1 I Bias C1 C C2 R1 L M2 Bias Yg = R1 = 1 −R1 − 1 sC1 (Cgs1 + CL)2 + sC2 ≈ (Cgs1 + CL)2 Cgs1 (gm1CL − GLCgs1 ) gm1Cgs1 CL gm1Cgs1 CL Cgs1 (gm1 CL − GLCgs1) Cgs1 CL ≈ C2 = C1 = (gm1 + GL)(Cgs1 + CL) (gm1 + GL)(Cgs1 + CL) Cgs1 + CL Single-T Gain Stages 5-43 Analog ICs; Jieh-Tsorng Wu Compensated Source Follower • Adding R1 and C1 to the input port can eliminate the complex poles. • For the compensated source follower, we have A(s) = [GS + s(CS + C2)] · Avg = RS gm1RL 1 + gm1RL × 1+ 1 − s/p1 Cgs1 sg m1 1 − s/p2 where p1 p2 Single-T Gain Stages = = − − GS ≈− Cgs1 CL CS + C gs1 +CL gm1 + GL Cgs1 + CL ≈− GS CS + Cgs1 gm1 + GL 5-44 CL if CL if CL Cgs1 Cgs1 Analog ICs; Jieh-Tsorng Wu Floating-Well Source Follower VDD V in Bias M2 p+ Vo V in Vo M1 p+ n+ N-Well M1 P-Substrate The follower is in an isolated well tied to the M1 source. Thus, VSB (M 1) = 0, and Avg (0) = gm1 gm1 + go1 + go2 • The junction capacitance at the M1’s source is now replaced by the well-substrate junction capacitor. • p+ guard-ring surrounding the n-well may be required. Single-T Gain Stages 5-45 Analog ICs; Jieh-Tsorng Wu Multiple-Transistor Gain Stages Jieh-Tsorng Wu ES A October 24, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Dominant-Pole Approximation The response of an amplifier has the form of m 2 1 + a 1 s + a2 s + · · · + am s N (s) ≈ A(s) = A(0) = A(0) 2 + · · · + b sn D (s) 1 + b1s + b2s s n 1−p A(0) s 1−p 1 If |p1| s ··· 1 − p n 2 |p2|, |p3|, · · · , |pn |, then p1 is a dominant pole. We have b1 = − 1 1 1 1 1 − − ··· − ≈− = p1 p2 pn p1 p1 A(0) |A(j ω)| = 1+ ω p1 2 1+ ω p2 ≈ 2 ··· 1 + ω pn −3 dB Bandwidth = ω−3dB ≈ |p1| ≈ Multiple-T Gain Stages 6-2 2 A(0) 1+ ω p1 2 1 b1 Analog ICs; Jieh-Tsorng Wu Zero-Value Time Constants i2 v2 C2 i1 v1 C1 η C3 v3 i3 • η is a linear active network without energy storage. • The b1 in the denominator of the system function can be expressed as b1 = T0 = R10C1 + R20C2 + R30C3 + · · · Ri 0 is the driving point resistance seen by Ci with all capacitors equal to zero. Multiple-T Gain Stages 6-3 Analog ICs; Jieh-Tsorng Wu Zero-Value Time Constant Example if R1 v s C v 1 C f R10 = R1 v o 1 gv m1 R 2 C R20 = R2 2 To determine Rf 0, replace Cf with a current source if , then v1 = if R1 Rf 0 = v1 − vo if vo = −(if + gmv1)R2 = R1 + R2 + gmR1R2 = R1 R2 1 + gmR2 + R1 We have b1 = Multiple-T Gain Stages T0 = R1C1 + R2C2 + (R1 + R2 + gmR1R2)Cf 6-4 Analog ICs; Jieh-Tsorng Wu Darlington Configuration VCC Bc VCC Cc Q1 Bc Cc M1 Q2 Q2 Ec Cc Bc c Ri v1 c Ro Ec VEE Ec c Gm v1 VEE For the BJT-BJT Darlington configuration, β = βo2(βo1 + 1) c Ric = rπ1 + (βo1 + 1)rπ2 c Gm = gm2 rπ 1 o1 +1)rπ 2 1 + (β c Ro = ro2 • Use to boost the effective current gain of BJTs. • No significant application in pure-MOS circuits. Multiple-T Gain Stages 6-5 Analog ICs; Jieh-Tsorng Wu BJT Cascode Configuration VCC RL VO + vo VBIAS Vi Q2 RS Q1 g m v2 i2 RS io Ct2 CL vo g m v1 vi v1 v2 Ct1 rπ1 rπ2 RL Ri n2 CL = Cµ2 + Ccs2 + Capacitive Load Ct2 = Cπ2 + Ccs1 rπ2 + rb2 αo2 rb2 1 = ≈ Ct1 = Cπ1 + Cµ1(1 + gm1Ri n2) Ri n2 = + gm2 βo2 + 1 gm2 βo2 + 1 • Usually IC2 ≈ IC1, then gm2 ≈ gm1 and Ct1 ≈ Cπ1 + 2Cµ1 . • If RL is large compared to ro2, then Ri n2 ≈ (1/gm2) 1 + RL/ro2 . Multiple-T Gain Stages 6-6 Analog ICs; Jieh-Tsorng Wu BJT Cascode Characteristics We can express voltage gain Av (s) as vo(s) v1 i2 io vo Av (s) = = = vi v1 i2 io vi (s) ⇒ Av (0) = −αo2 gm1RL rπ1 1 s RS + rπ1 1 − p × (−gm1 ) × 1 αo2 2 (1 − s/p1 )(1 − s/p2 )(1 − s/p3 ) 1 1 gm2 p1 = − p2 = − αo2 Ct2 (RS rπ1)Ct1 RS + rπ1 s 1− p 3 Av (0) Av (s) = rπ1 × s 1− p RL p3 = − 1 RLCL The output resistance of the cascode stage is Rout = ro2 · 1 + gm2ro1 1 + Multiple-T Gain Stages 1+ 1 βo 2 + 1 g m2 ro 2 g m2 ro 1 βo 2 6-7 = ro2 1 + 1 + gm2ro1 1+ g m2 ro 1 βo 2 ≈ βo2ro2 Analog ICs; Jieh-Tsorng Wu MO...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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