Analog Integrated Circuits (Jieh Tsorng Wu)

To minimize voss want vds 3 vds 4 vgs 6 then wl3 wl6

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Unformatted text preview: = − C1 CMRR = CMRR Acm = Gcm · Z1 = Gmd Gmc 2gm1gm3 · (1 − s/zm)(1 − s/pt ) go5(go1 + go3) (1 − s/zt )(1 − s/zc) CMRR(∞) = gm1/2 1 = gm1 2 ω z Opamp-I t p o z c p m z p mt 13-11 Analog ICs; Jieh-Tsorng Wu Simplified Two-Stage Model Cc vo v1 gm1vi R1 G1 = go2 + go4 gm6v1 C1 G2 = go6 + go7 R2 C1 C2 Cgs6 vo 1 − s/z1 Av ≡ = Av (0) vi (1 − s/p1 )(1 − s/p2) Av (0) = gm1gm6R1R2 gm1 1 p1 ≈ − × Cc Av (0) Opamp-I p2 ≈ − 13-12 gm6 C1 + C2 z1 = + gm6 Cc Analog ICs; Jieh-Tsorng Wu Frequency Compensation Using Nulling Resistor VDD M14 M3 M13 M4 M6 M16 M15 M10 Vi M1 M2 Cc Vo Vi VB1 M12 Opamp-I M7 M11 R VSS M5 B VSS VB2 13-13 Analog ICs; Jieh-Tsorng Wu Frequency Compensation Using Zero-Nulling Resistor • The zero-nulling resistor Rc is realized by M10 in the triode region. z1 = • Let (W/L)13 (W/L)14 = (W/L)15 (W/L)16 and 1 (1/gm6 − Rc)Cc (W/L)7 (W/L)11 Vov 6 = Vov 13 = Vov 14 gm6Rc = = (W/L)6 , (W/L)13 =− gm6 (gm6 Rc − 1)Cc then Vov 10 = Vov 15 = Vov 16 Vov 6 Vov 10 gm6 (W/L)6 Vov 6 (W/L)6 = = gm10 (W/L)10 Vov 10 (W/L)10 = Vov 13 Vov 15 = (W/L)15 (W/L)13 (W/L)15 (W/L)13 • p2/z1 ≈ (gm6Rc − 1)Cc /(C1 + C2) is independent of process and temperature variations. Opamp-I 13-14 Analog ICs; Jieh-Tsorng Wu Voltage and Current Range Input Common-Mode Range Vi c(max) = VDD − VGS 3 + Vt1 Vi c(mi n) = VSS + VDSAT 5 + VGS 1 • The range is limited to the voltage levels where any transistor goes out of saturation. Output Voltage Range Vo(max) = VDD − VDSAT 6 Vo(mi n) = VSS + VDSAT 7 • Output resistive load can also limit the voltage range, if the available output current is insufficient. Maximum Output Current Io(sink,max) = ID7 1 W Io(source,max) = kp 2 L [Vgs6(max) − Vt6 ]2 − ID7 6 Vgs6(max) = VDD − Vi + + Vt2 Opamp-I 13-15 Analog ICs; Jieh-Tsorng Wu Slew Rate VDD M3 V M4 I x Vo M6 i Vi V M1 M2 Vi Io Cc Vo C2 i VB1 ISS M7 t VSS Exponential Log (SR) Vo SR ext SR int SR Opamp-I t Log (C 2 ) 13-16 Analog ICs; Jieh-Tsorng Wu Slew Rate The internal slew rate is generally limited by current available to charge and discharge Cc from input stage. Therefore, SRi nt = d Vo dt = max Ix(max) Cc = ISS Cc = ISS ISS gm1 × = × ωu gm1 gm1 Cc = (VGS 1 − Vt1 ) × ωu = Vov 1 × ωu The external slew rate is limited by the available current to charge and discharge C2. Thus, ID7 − Ix (max ) ID7 − ISS SRext = = C2 C2 Opamp-I 13-17 Analog ICs; Jieh-Tsorng Wu Settling Time The frequency response and step response of a single-pole amplifier is A(s) = Ao 1 + s/ωp Vo(t ) = Ao 1 − e−ωpt The settling time can be written as 1 1 Ao 1 ln = ln ts ( ) = ωp ωu • ωu = Ao · ωp is the dominant-pole unity-gain frequency. • = 1 − |Vo(ts )/Ao | is the error when settling occurs. The 10% to 90% rise time is tr = Opamp-I 1 2.2 0.35 ln(9) = = ωp ωp fp 13-18 ωp = 2πfp Analog ICs; Jieh-Tsorng Wu Input Impedance Cin- C VDD Vo Cd Cin+ M3 C M4 M6 Vi Ct C gd2 M2 g m2 Vo VB1 Cc Vi Cc Vo M5 M7 VSS R2 Opamp-I M2 R1 M6 Vi M1 13-19 Analog ICs; Jieh-Tsorng Wu Input Impedance Shorting the noninverting input to ground, Ci n− = Cd + C− ≈ Cgs1 2 Shorting the inverting input to ground, Ci n+ = Cd + C+ ≈ And we have Cd ≈ Opamp-I Cgs2 2 Cgs1 2 + Cgd 2 · (1 + Ao1 ) C− ≈ 0 Ao1 = gm2R1 C+ ≈ Cgd 2 · (1 + Ao1) 13-20 Analog ICs; Jieh-Tsorng Wu Input Impedance The equivalent voltage gain of the M2 stage decreases with increasing frequency, due the the effect of Ct . The capacitance C+ is then modified as C+ ≈ Cgd 2 · Ao1 · 1+ 1+ Cgd 2 g m2 s Cgd 2 +Ct Ao1 g s m2 where Ct = Cgs6 + Cc · (1 + Ao2) = Cgs6 + Cc · (1 + gm6R2) • For gm2/[Ao1 (Cgd 2 + Ct )] < ω < gm2/Cgd 2 , C+ become resistive, and C+ Opamp-I → 1 R+ ≈ · gm2 13-21 1+ Ct Cgd 2 Analog ICs; Jieh-Tsorng Wu Output Impedance Log |Zo| Cc R2 v1 R1 C1 gm6v1 R2 1/gm6 Zo |p1 | with unity-gain feedback Assuming gm6 |z1| ωu |p | Log f 2 R1 and R2, we have Zo = R2 · 1 + sR1 (Cc + C1) 1 + sgm6R1R2 Cc + s2 R1C1R2Cc gm6 gm1 1 1 1 p2 ≈ − p1 ≈ − =− · z1 ≈ − gm6R1 R2Cc Cc |Av (0)| C1 R1(Cc + C1) Opamp-I 13-22 Analog ICs; Jieh-Tsorng Wu Output Impedance • For frequencies larger than z1, Cc acts as a short, the Zo is a resistive 1/gm6. • The closed-loop Zo of the unity-gain buffer is Zoc ≈ Zo Av ≈ R2 Av (0) · (1 − s/z1 ) for ω < ωu where ωu = gm1/Cc. Opamp-I 13-23 Analog ICs; Jieh-Tsorng Wu Systematic Input Offset Voltage VDD M3 M4 V1 VY M6 VOS Vi M1 M2 Vi Cc Vo ISS VB1 M5 M7 12 ID = kVov (1 + λVDS ) 2 λ3 = λ4 λ1 = λ2 ISS λ1(VY − V1) 2 ISS λ3(V1 − VY ) ∆I3−4 = |ID3| − |ID4| = 2 ∆I1−2 = ID1 − ID2 = VSS The systematic input referred dc offset can be expressed as −VOS,s Opamp-I Vov,1−2 1 · (λ1 + λ3)(VY − V1) = · (∆I1−2 − ∆I3−4) = gm1 2 13-24 Analog ICs; Jieh-Tsorng Wu Systematic Input Offset Voltage • The systematic offset is caused by asymmetry in the dc biasing of VY and V1. • To minimize VOS,s , want VDS 3 = VDS 4 = VGS 6 , then (W/L)3 (W/L)6 = (W/L)4 (W/L)6 = (W/L)5 2...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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