Unformatted text preview: = −
C1
CMRR = CMRR Acm = Gcm · Z1 = Gmd
Gmc
2gm1gm3 · (1 − s/zm)(1 − s/pt ) go5(go1 + go3) (1 − s/zt )(1 − s/zc)
CMRR(∞) = gm1/2 1
=
gm1
2 ω
z OpampI t p
o z c p
m z p
mt 1311 Analog ICs; JiehTsorng Wu Simpliﬁed TwoStage Model
Cc
vo v1
gm1vi R1 G1 = go2 + go4 gm6v1 C1 G2 = go6 + go7 R2 C1 C2 Cgs6 vo
1 − s/z1
Av ≡
= Av (0)
vi
(1 − s/p1 )(1 − s/p2)
Av (0) = gm1gm6R1R2
gm1
1
p1 ≈ −
×
Cc
Av (0)
OpampI p2 ≈ − 1312 gm6
C1 + C2 z1 = + gm6
Cc Analog ICs; JiehTsorng Wu Frequency Compensation Using Nulling Resistor
VDD M14 M3 M13 M4
M6 M16 M15 M10
Vi M1 M2 Cc Vo Vi
VB1 M12 OpampI M7 M11
R VSS M5 B VSS
VB2 1313 Analog ICs; JiehTsorng Wu Frequency Compensation Using ZeroNulling Resistor
• The zeronulling resistor Rc is realized by M10 in the triode region.
z1 = • Let (W/L)13
(W/L)14 = (W/L)15
(W/L)16 and 1
(1/gm6 − Rc)Cc (W/L)7
(W/L)11 Vov 6 = Vov 13 = Vov 14 gm6Rc = = (W/L)6
,
(W/L)13 =− gm6
(gm6 Rc − 1)Cc then Vov 10 = Vov 15 = Vov 16 Vov 6
Vov 10 gm6
(W/L)6 Vov 6
(W/L)6
=
=
gm10 (W/L)10 Vov 10 (W/L)10 = Vov 13
Vov 15 = (W/L)15
(W/L)13 (W/L)15
(W/L)13 • p2/z1 ≈ (gm6Rc − 1)Cc /(C1 + C2) is independent of process and temperature
variations.
OpampI 1314 Analog ICs; JiehTsorng Wu Voltage and Current Range
Input CommonMode Range
Vi c(max) = VDD − VGS 3 + Vt1 Vi c(mi n) = VSS + VDSAT 5 + VGS 1 • The range is limited to the voltage levels where any transistor goes out of saturation.
Output Voltage Range
Vo(max) = VDD − VDSAT 6 Vo(mi n) = VSS + VDSAT 7 • Output resistive load can also limit the voltage range, if the available output current is
insuﬃcient.
Maximum Output Current
Io(sink,max) = ID7 1
W
Io(source,max) = kp
2
L [Vgs6(max) − Vt6 ]2 − ID7
6 Vgs6(max) = VDD − Vi + + Vt2
OpampI 1315 Analog ICs; JiehTsorng Wu Slew Rate
VDD M3
V M4 I
x Vo M6 i
Vi
V M1 M2 Vi Io Cc Vo
C2 i
VB1 ISS M7 t
VSS
Exponential Log (SR) Vo SR ext
SR int
SR OpampI t Log (C 2 ) 1316 Analog ICs; JiehTsorng Wu Slew Rate
The internal slew rate is generally limited by current available to charge and discharge
Cc from input stage. Therefore,
SRi nt = d Vo
dt =
max Ix(max)
Cc = ISS
Cc = ISS
ISS
gm1
×
=
× ωu
gm1
gm1
Cc = (VGS 1 − Vt1 ) × ωu = Vov 1 × ωu The external slew rate is limited by the available current to charge and discharge C2.
Thus,
ID7 − Ix (max ) ID7 − ISS
SRext =
=
C2
C2 OpampI 1317 Analog ICs; JiehTsorng Wu Settling Time
The frequency response and step response of a singlepole ampliﬁer is
A(s) = Ao
1 + s/ωp Vo(t ) = Ao 1 − e−ωpt The settling time can be written as
1
1 Ao 1
ln =
ln
ts ( ) =
ωp
ωu
• ωu = Ao · ωp is the dominantpole unitygain frequency.
• = 1 − Vo(ts )/Ao  is the error when settling occurs. The 10% to 90% rise time is
tr = OpampI 1
2.2 0.35
ln(9) =
=
ωp
ωp
fp
1318 ωp = 2πfp Analog ICs; JiehTsorng Wu Input Impedance
Cin C VDD
Vo Cd
Cin+ M3 C M4
M6 Vi Ct
C gd2 M2
g
m2 Vo VB1 Cc Vi Cc Vo M5
M7
VSS R2 OpampI M2 R1
M6 Vi M1 1319 Analog ICs; JiehTsorng Wu Input Impedance
Shorting the noninverting input to ground,
Ci n− = Cd + C− ≈ Cgs1
2 Shorting the inverting input to ground,
Ci n+ = Cd + C+ ≈
And we have
Cd ≈ OpampI Cgs2
2 Cgs1
2 + Cgd 2 · (1 + Ao1 ) C− ≈ 0 Ao1 = gm2R1 C+ ≈ Cgd 2 · (1 + Ao1) 1320 Analog ICs; JiehTsorng Wu Input Impedance
The equivalent voltage gain of the M2 stage decreases with increasing frequency, due
the the eﬀect of Ct . The capacitance C+ is then modiﬁed as C+ ≈ Cgd 2 · Ao1 · 1+
1+ Cgd 2
g m2 s Cgd 2 +Ct
Ao1 g
s
m2 where
Ct = Cgs6 + Cc · (1 + Ao2) = Cgs6 + Cc · (1 + gm6R2)
• For gm2/[Ao1 (Cgd 2 + Ct )] < ω < gm2/Cgd 2 , C+ become resistive, and C+ OpampI → 1
R+ ≈
·
gm2 1321 1+ Ct
Cgd 2 Analog ICs; JiehTsorng Wu Output Impedance
Log Zo Cc
R2
v1 R1 C1 gm6v1 R2 1/gm6
Zo p1  with unitygain feedback Assuming gm6 z1 ωu p  Log f
2 R1 and R2, we have
Zo = R2 · 1 + sR1 (Cc + C1) 1 + sgm6R1R2 Cc + s2 R1C1R2Cc
gm6
gm1
1
1
1
p2 ≈ −
p1 ≈ −
=−
·
z1 ≈ −
gm6R1 R2Cc
Cc Av (0)
C1
R1(Cc + C1)
OpampI 1322 Analog ICs; JiehTsorng Wu Output Impedance
• For frequencies larger than z1, Cc acts as a short, the Zo is a resistive 1/gm6.
• The closedloop Zo of the unitygain buﬀer is
Zoc ≈ Zo
Av ≈ R2
Av (0) · (1 − s/z1 ) for ω < ωu where ωu = gm1/Cc. OpampI 1323 Analog ICs; JiehTsorng Wu Systematic Input Oﬀset Voltage
VDD M3 M4 V1 VY M6 VOS
Vi M1 M2 Vi Cc Vo ISS
VB1 M5 M7 12
ID = kVov (1 + λVDS )
2
λ3 = λ4
λ1 = λ2
ISS
λ1(VY − V1)
2
ISS
λ3(V1 − VY )
∆I3−4 = ID3 − ID4 =
2
∆I1−2 = ID1 − ID2 = VSS The systematic input referred dc oﬀset can be expressed as
−VOS,s OpampI Vov,1−2
1
· (λ1 + λ3)(VY − V1)
=
· (∆I1−2 − ∆I3−4) =
gm1
2 1324 Analog ICs; JiehTsorng Wu Systematic Input Oﬀset Voltage
• The systematic oﬀset is caused by asymmetry in the dc biasing of VY and V1.
• To minimize VOS,s , want VDS 3 = VDS 4 = VGS 6 , then
(W/L)3
(W/L)6 = (W/L)4
(W/L)6 = (W/L)5
2...
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 Winter '09
 Choma
 Integrated Circuit, Transistor, The Land, Bipolar junction transistor, VDS, Analog ICs, JiehTsorng Wu

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