Analog Integrated Circuits (Jieh Tsorng Wu)

Velocity saturation eects are insignicant in hand

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Unformatted text preview: vd = Carrier Drift velocity = µE Ec ≈ 1.5 × 106 V/m 1 + E /E c • µ is the low-field mobility. In the triode region ID = W QI (y ) · vd MOST ⇒ ID = µCox 1+ 3-20 1 VDS Ec L W · L (VGS − Vt )VDS 12 − VDS 2 Analog ICs; Jieh-Tsorng Wu Carrier Velocity Saturation Using ∂ID /∂VDS = 0 to find VDSAT , we have VDSAT = EcL 1 + 2Vov Ec L − 1 = Vov 1 − Vov 2EcL + ··· And the saturation current is IDSAT Vov 1 1 W2 W2 + ··· = µCox VDSAT = µCox Vov 1 − 2 2 L L 2EcL 2 The transconductance is gm = W µCox Ec MOST 1+ 2Vov Ec L 1+ −1 2Vov Ec L or gm = ID 3-21 2 Ec L 1 + 2Vov Ec L 1+ 2Vov Ec L −1 Analog ICs; Jieh-Tsorng Wu Effects of Carrier Velocity Saturation • If Vov EcL, IDSAT ≈ 1 µCox W 2 V Vov L ov 21 + gm ≈ µCox Ec L W Vov L 1 + Vov EL gm 2 ≈ ID Vov c 111 – The mobility degradation can be modeled by a resistor RSX = E µC W in series ox c with the source of an ideal square-law device. – Velocity-saturation effects are insignificant in hand calculations if Vov < 0.1EcL. • If Vov EcL, IDSAT ≈ µCox W Vov Ec = W Cox Vov vscl gm ≈ W Cox vscl gm 1 ≈ ID Vov – vscl = µEc is the scattering-limited velocity. – IDSAT is a linear function of Vov , and independent of L. MOST 3-22 Analog ICs; Jieh-Tsorng Wu Hot Carriers IDB = K1(VDS − VDSAT )ID e−K2/(VDS −VDSAT ) gd b −1 • K1 ∼ 5 V MOST ∂IDB IDB ≡ = ∂VD VD − VDSAT VDS K2 IDB K2 +1 ≈ − VDSAT (VDS − VDSAT )2 and K2 = 30 V are process-dependent parameters. 3-23 Analog ICs; Jieh-Tsorng Wu Short-Channel Effects • Hot Carriers. – The drain-to-substrate current can be modeled by a finite drain-to-substrate resistor. – The punch-through current is an additional cause of lower ro and possibly transistor breakdown. – Some charges in the gate current can be trapped in the gate oxide, causing a shift in Vt . – The host-carrier effects are more pronounced for nMOST than for pMOST, because electrons have larger velocities than holes. • Drain-Induced Barrier Lowering (DIBL) – For short-channel devices, DIBL effectively lowers Vt as VDS is increased, thereby further lowering the ro. • Carrier Velocity Saturation. MOST 3-24 Analog ICs; Jieh-Tsorng Wu Subthreshold Conduction in MOST gm/ ID 1 Weak Inv. Asymptote n UT Strong Inv. Asymptote Moderate 0 0.01 0.1 Weak 1 10 Strong 100 I D / ( I tW/L) In the weak inversion region W Vov /(nUT ) ID = It e 1 − e−VDS /UT L n= Cox + Cd epl Cox = 1 + χ ≈ 1. 5 • It ∝ Dnnpo depends on process parameters (e.g., 20 nA). MOST 3-25 Analog ICs; Jieh-Tsorng Wu Subthreshold Conduction in MOST When |VDS | > 3UT , ID saturates and Cox ∂ID ID ID gm ≡ = = ∂VGS nUT UT Cox + Cd epl Cox gm 1 1 = = ID nUT UT Cox + Cd epl To find Vov for strong inversion, let gm 1 2 = = ID nUT Vov • 2nUT < Vov 0 < Vov < 2nUT Vov < 0 • In weak inversion, Cgs ⇒ Vov = 2nUT ≈ 78 mV → Strong Inversion → Moderate Inversion → Weak Inversion Cgd 0, and Cgb = W L × (Cox Cd epl ) = W L × Cox Cd epl /(Cox + Cd epl ) MOST 3-26 Analog ICs; Jieh-Tsorng Wu Integrated Circuit Technologies Jieh-Tsorng Wu ES A July 16, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Integrated-Circuit NPN Transistor Emitter Diffusion Base Diffusion Isolation Diffusion Epitaxial layer Buried layer P-Substrate 0.5–2.5 µm, 2–10 Ω/ 1–3 µm, 100–300 Ω/ 20–40 Ω/ 17 µm (BVCE O = 36 V) 15 3 10 atoms/cm , 5 Ω-cm 20–50 Ω/ 250 µm 16 3 10 atoms/cm 1–2 Ω-cm • Junction isolation. Technologies 4-2 Analog ICs; Jieh-Tsorng Wu Lateral PNP Transistor • Lightly doped base. • Slow. • Low current gain, especially as IC ↑. Technologies 4-3 Analog ICs; Jieh-Tsorng Wu Vertical PNP Transistors • Low base resistance. • Low emitter-base breakdown voltage. • Substrate collector (no buried layer). Technologies 4-4 Analog ICs; Jieh-Tsorng Wu Advanced-Technology NPN Transistor Emitter Base Epitaxial layer Buried layer P-Substrate 0.1 µm 0.1 µm 1 µm, 0.5 Ω-cm 20–50 Ω/ 250 µm 16 3 10 atoms/cm 1–2 Ω-cm • Oxide isolation. • Polysilicon emitter self-aligned structure. • High fT (> 10 GHz). Technologies 4-5 Analog ICs; Jieh-Tsorng Wu Base and Emitter Diffused Resistors Technologies 4-6 Analog ICs; Jieh-Tsorng Wu Base Pinch Resistor Technologies 4-7 Analog ICs; Jieh-Tsorng Wu Epitaxial Resistor Technologies 4-8 Analog ICs; Jieh-Tsorng Wu Properties of IC Resistor Technologies 4-9 Analog ICs; Jieh-Tsorng Wu Capacitors • PN junctions. • Metal or poly over thin oxide. Technologies 4-10 Analog ICs; Jieh-Tsorng Wu Diodes (a) (b) (c) (d) • Implementation (a) is usually preferred to avoid forward biasing the C-B junction. • C-B forward bias injects carriers into the epi, which in turn can be collected in the substrate. Technologies 4-11 Analog ICs; Jieh-Tsorng Wu CMOS Integrated-Circuit Technologies 0.5 µm CMOS M2 1.20 M1 0.60 Poly 0.25 Field Oxide 0.30 Gate Oxide 130 n+ Depth 0.20 p+ Depth 0.25 N-well Depth 2.50 µm µm µm µm Å µm µm µm • Additional polysilicon layer may exist to realize poly-to-poly capacitors. • There ar...
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