Analog Integrated Circuits (Jieh Tsorng Wu)

Wla2vov rl vi 1 w gm k vov l 1 vosp vosn 2

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Unformatted text preview: + 6 UT 3 + ··· = a1vi + a2vi2 + a3vi3 + · · · ˆ Let vi = vi sin ωt , then the harmonic distortion factors are ˆ 1 a2 1 vi ˆi = ·v HD2 = 2 a1 4 UT ˆ 1 a3 2 1 vi ˆ HD3 = ·v = 4 a1 i 24 UT Output Stages 10-13 2 Analog ICs; Jieh-Tsorng Wu Class-A MOST Common-Source Stage Vo = IoRL = (IQ − Id 1) RL VDD Id 1 M2 IQ 2 Let Vi = VI + vi , VI = Vov + Vt and IQ = (1/2)kVov Io Vo Vi M1 1 1 W 2 = µCox (Vi − Vt ) = k (Vi − Vt )2 2 2 L RL 1 Vo = RL (IQ − Id ) = RL IQ − k (Vov + vi )2 2 = −RLIQ VDD vi 2 Vov vi + Vov 2 ˆ Let vi = vi sin ωt , then the harmonic distortion factors are 1 a2 1 vi ˆi = ·v HD2 = 2 a1 4 Vov Output Stages 10-14 HD3 = 0 Analog ICs; Jieh-Tsorng Wu Class-B Push-Pull Emitter Follower VCC Q1 Io Vi Vo Q2 RL VCC Output Stages 10-15 Analog ICs; Jieh-Tsorng Wu Output Power of Class-B Push-Pull Emitter Follower For a sinusoidal output ˆ Vo = Vo sin ωt Io = Vo/RL = Iˆo sin ωt We have ˆ2 1ˆ ˆ 1 Vo PL = VoIo = 2 2 RL Isupply = 1 T /2 T /2 0 ˆ 2 Vo 2 Ic1(t )d t = = Iˆo π RL π Psupply = VCC Isupply Vce1 = VCC − Ic1RL 2 VCC ˆ = ·V π RL o ˆ π Vo π Power Conversion Efficiency = ηC = ≤ 4 VCC 4 Output Stages 10-16 Analog ICs; Jieh-Tsorng Wu Class-AB Push-Pull Emitter Followers VCC VCC VCC IB1 IB1 Q1 VB1 V1 Q1 Q1 Q3 IQ Q3 V1 Vo VB2 Vo IQ1 Q4 Q4 R1 Q2 VEE Q2 Q2 Vi Vi Q5 Q5 VEE VBE 1 + |VBE 2 | = VBE 3 + |VBE 4 | Output Stages Vo IQ2 ⇒ VEE IQ1 = IB1 10-17 IS 1 IS 2 IS 3 IS 4 IQ2 = IC3 IC4 IS 1IS 2 IS 3IS 4 Analog ICs; Jieh-Tsorng Wu Class-AB Push-Pull Source Followers VDD VDD IB1 Vi M5 M6 M1 M3 M3 V1 IQ1 Vo M1 V1 Vo IQ2 M4 M2 Vi M5 IB1 VSS VSS VGS 1 + |VGS 2 | = VGS 3 + |VGS 4 | Output Stages Q2 Q4 ⇒ IQ1 = IB1 10-18 1/ kn(W/L)3 + 1/ kp(W/L)4 1/ kn(W/L)1 + 1/ kp(W/L)2 2 Analog ICs; Jieh-Tsorng Wu Class-AB Push-Pull Common-Source Stage VDD 2IB1 M11 VDD IB M12 V2 M1 R1 IB3 IQ Vo V2 M1 V bop M3 V bon M4 V1 Vi IQ M2 V1 M2 Vo M14 M5 VSS Vi M5 IB2 M13 VSS Output Stages 10-19 Analog ICs; Jieh-Tsorng Wu Class-AB Push-Pull Common-Source Stage Let IB1 = IB2 = IB3 , and 1 K W L = 1 W L 11 W L = 3 W L 12 1 K W L = 2 W L 13 W L = 4 W L 14 Then, VGS 1 = VGS 11, VGS 3 = VGS 12, VGS 2 = VGS 13, VGS 4 = VGS 14, and IQ = ID1 = ID2 = K · IB1 • M3 and M4 form a floating resistor. • Large output impedance. The pole at Vo can be significant. • Large distortion. Usually this output stage is included in the feedback loop. Output Stages 10-20 Analog ICs; Jieh-Tsorng Wu Class-AB Quasi-Complementary Configuration VDD EP gm1vgs1 EP M1 vgs1 g o1 io Io Vi Vo Vi vo RL M2 EN EN g o2 gm2vgs2 VSS io Go = − vo vgs2 vi =0 = gm1AE P + gm2AE N + go1 + go2 • The distortion and output resistance are reduced by AE P and AE N . • Need to control IQ . Output Stages 10-21 Analog ICs; Jieh-Tsorng Wu Class-AB Quasi-Complementary Configuration AE P = AE N = A VDD VOSP EP Vtn = −Vtp = Vt M1 Io kp Vo Vi EN = kn 1 W L =k 2 W L 1W Id 1 = − k (Vgs1 + Vt )2 2L 1W Id 2 = k (Vgs2 − Vt )2 2L RL VOSN W L M2 VSS If Vi = 0 and VOSP = VOSN = 0, let −ID1 = ID2 = IQ Output Stages Vov = 2IQ k (W/L) Vgs1 = −Vt − Vov 10-22 Vgs2 = Vt + Vov Analog ICs; Jieh-Tsorng Wu Class-AB Quasi-Complementary Configuration We have Vgs1 = −Vt − Vov + A[Vo − (Vi − VOSP )] Vo Io = RL Io + Id 1 + Id 2 = 0 Vgs2 = Vt + Vov + A[Vo − (Vi − VOSP )] ⇒ Vo = VOSP +VOSN 2 1 k (W/L)A[2Vov −A(VOSP −VOSN )]RL Vi − 1+ • If VOSP = VOSN = 0, Vo = • If A(VOSP − VOSN ) Vo = Output Stages Vi 1+ 1 k (W/L)A2Vov RL = Vi 1 + 2Ag1 R mL 2Vov and 2AgmRL VOSP +VOSN 2 1 k (W/L)A2Vov RL Vi − 1+ = W gm = k Vov L 1, VOSP +VOSN 2 + 2Ag1 R mL Vi − 1 10-23 ≈ Vi − VOSP + VOSN 2 Analog ICs; Jieh-Tsorng Wu Class-AB Quasi-Complementary Configuration To find IQ when VOSP and VOSN exist, let Vi = 0 and Vo + VOSP ≈ VOSP − VOSN Vo + VOSN ≈ − 2 1W IQ = k 2L Vov − A VOSP − VOSN VOSP − VOSN 2 2 2 Define IQ0 = IQ when VOSP = VOSN = 0, and ∆IQ = IQ0 − IQ , VOSP − VOSN 1W ∆IQ = k A(VOSP − VOSN ) Vov − A 2L 4 VOSP − VOSN ∆IQ =A IQ0 Vov 1−A VOSP − VOSN 4Vov ≈A VOSP − VOSN Vov • Must keep A small to reduce IQ variation. Output Stages 10-24 Analog ICs; Jieh-Tsorng Wu An Error Amplifier Example Let VDD M17 M15 (W/L)15 = (W/L)16 = (W/L)17 M16 A (W/L)13 = (W/L)14 M1 ISS M14 M13 VSS ⇒ IQ(M 1) = ISS × VSS C1 VSS (W/L)1 (W/L)17 ID13 = ID14 = ISS − IBB /2 Vi Vo M12 M11 Voltage gain is IBB EP VSS AE P gm11 = gm14 + gmb14 • Want large swing at node A to provide strong gate drive for M1. • Reference: Khorramabadi, JSSC 4/92, pp. 539–544. Output Stages 10-25 Analog ICs; Jieh-Tsorng Wu Combined Common-Drain Common-Source Configuration VDD IB1 IB2 VOS M1 VDD EP M3 M11 V1 Io Vo RL M4 M2 Vi Vi M5 EN M6 VOS M12 VSS VSS Output Stages 10-26 Analog ICs; Jieh-Tsorng Wu Combined Common-Drain Common-Source Configuration • VOS can be introduced by intentionally mismatching the input differential pair in each error amplifier. • The circuit can be designed so that, when Vo = V1 = 0, the introduction of VOS turn off M11 and M12. • M11 is turned on only when V1 − Vo − VOS > |Vtp |/AE P . • Error amplifiers, AE P and AE N , can have high gain, and are often designed as onestage amplifier with gain ≈ gmro. • The wide bandwidth of M1 and M2 source followers simplify the design required to guarantee stability. • The V1 voltage range, limited by Vgs3 and Vgs4 , can be in...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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