Analog Integrated Circuits (Jieh Tsorng Wu)

We have w i 1 h i 1 ai 1tran ai tran nt p

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ing selection of unit cells. DACs 24-24 Analog ICs; Jieh-Tsorng Wu A Current Cell Example Cj SEL Ri R i+1 Local Decoder Io1 CLK Io2 V1 M1 M2 Va V1 V2 SEL V2 VB1 M3 t VSS • The current switch MOSTs, M1 and M2, are in the triode region when fully turned on. • To minimize voltage fluctuation at Va, the inverters are sized so that the cross-over voltage of the V1 and V2 transient waveforms can turn on both M1 and M2. • Reference: C-H Lin and K Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” JSSC, 12/1998, pp. 1948–1958. DACs 24-25 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution DACs 1 Vo N-1 2 C bN-1 2 2C b2 1 2C b1 0 2C C Cp b0 Vref 1 N 2C Vo 2 bN-1 N-1 2 2C C b2 1 2C b1 0 2C b0 Vref DACs 24-26 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution DACs During φ1 = 1, Vo = 0 Cap Bottom Plate @ GND During φ2 = 1, bi = 1 0 → Cap Bottom Plate @Vref → Cap Bottom Plate @GND Vo = Vref C × × NC + C 2 p N −1 bi 2i i =0 • Binary-weighted or equally-weighted capacitor array. • Cp is top plate parasitic capacitance, and introduces a gain error. • Opamp can be used to provide voltage gain and mitigate the effects of Cp. • DACs at resolutions of 10 bits or above usually requires some kind of trimming or calibration. DACs 24-27 Analog ICs; Jieh-Tsorng Wu Segmented DAC Architecture Din N −1 N M M-Bit DAC L L-Bit DAC Di n = AM M −1 bi 2i = i =0 bi +L2i +L + i =0 L−1 bj 2j j =0 M −1 AL AM = ∆M × L−1 bi +L2i AL = ∆L × i =0 M −1 Ao = AM + AL = ∆L × j =0 N =M +L Ao bi +L2i +L + ∆L × i =0 ∆ M = 2L × ∆ L L−1 N −1 bj 2j = ∆L × j =0 bj 2j bi 2i i =0 • The M-DAC need to have ±∆L/2 accuracy. • Signal path delay mismatch between the M-DAC and the L-DAC can cause glitch. • Can have more than two segments. DACs 24-28 Analog ICs; Jieh-Tsorng Wu A 10-Bit Segmented Current-Steering DAC B4-B6 B0-B3 B4-B6 Column Decoder 8x8 8x8 Row Decoder B7-B9 Row Decoder Column Decoder B7-B9 Io 8x8 8x8 Column Decoder B7-B9 Column Decoder B4-B6 DACs Row Decoder B7-B9 Row Decoder Io B4-B6 24-29 Analog ICs; Jieh-Tsorng Wu A 10-Bit Segmented Current-Steering DAC • Segmented 6-2-2 architecture with common-centroid layout. • Each current cell in the matrix contains 4 LSB current. • Reference: J. Bastos, et. al., “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” JSSC 12/1998, pp. 1959–1969. DACs 24-30 Analog ICs; Jieh-Tsorng Wu A Segmented Current-Steering DAC Io VB I I VB VC I 4X VB 2X 1X 1X L M M-DAC Thermometer Decoder L-DAC Binary Decoder N Din • Greatly reduces area for large N while ensuring monotonicity (at least for MSBs). • The L-DAC can be a binary-weighted DAC if its glitches can be tolerated. • Reference: H. Schouwenaar, et al., JSSC 12/88, pp. 1290–1297. DACs 24-31 Analog ICs; Jieh-Tsorng Wu Dynamically-Matched Current Sources Out Io Iref Calibration Switch Array Cs Cs Cs Iref Cs M1 S1 VSS Iref IB1 Cs VSS Out Out Iref VB2 M3 Operation M4 Iref Cbr MC1 Cbr M1 MS1 MS1D M1 M2 IB1 VB1 S1 Cs VSS VSS DACs 24-32 Analog ICs; Jieh-Tsorng Wu Dynamically-Matched Current Sources • The bias voltage for the current sources is stored in each individual Cs . The voltage on Cs is refreshed periodically by means of calibration. • A spare current source can be added to facilitate uninterrupted operation. • Cs can be just the Cgs of M1. • The switching error of MS1 as well as gm1 must be minimized. • By adding M2 with a constant current, gm1 can be reduced. • 16-bit resolution can be achieved using this technique. • Reference: D. Groeneveld, et al., JSSC 12/89, pp. 1517–1522. DACs 24-33 Analog ICs; Jieh-Tsorng Wu A Segmented Charge-Redistribution DAC L-DAC M-DAC Vo Vx 2 2C bj 1 2C 0 2C C bi L Vref Vref Di n = bi 2i i =0 DACs C M N −1 Vo = C Vref 2M M −1 · i =0 N =M +L Vx = Vref 2L L−1 · bj 2j j =0 M −1 L−1 Vref Vref N −1 1 bi +L2i + · Vx = · bi +L2i +L + bj 2j = · bi 2i 2M 2M + L 2N i = 0 i =0 j =0 24-34 Analog ICs; Jieh-Tsorng Wu A Capacitor-Resistor Hybrid DAC M 2C M-DAC 2 bi M-1 2 2C C 1 2C Vo 0 2C 0 2C M Vref L-DAC bj Vo = DACs Vref 2M M −1 × i =0 L Vref Vref L−1 Vref N −1 1 bi +L2i + × × bj 2j = × bi 2i 2M 2L 2N j =0 i =0 24-35 N =M +L Analog ICs; Jieh-Tsorng Wu A Resistor-Capacitor Hybrid DAC 1 L 2C L-DAC 2 2C L-1 2 C bj Vo 1 2C 0 2C L V2 V1 M-DAC bi M Vref M −1 V1 = ∆M × bi +L2 i V2 = V1 + ∆M i =0 DACs 24-36 ∆M = Vref 2M N =M +L Analog ICs; Jieh-Tsorng Wu A Resistor-Capacitor Hybrid DAC During φ1 = 1, Vo = 0 Cap Bottom Plate @ GND During φ2 = 1, bi = Vo = V1 + ∆M 2L L−1 × bj 2j = j =0 1 0 Vref 2M → Cap Bottom Plate @V2 → Cap Bottom Plate @V1 M −1 × bi +L2i + i =0 Vref 2M + L L−1 × bj 2j = j =0 Vref 2N N −1 × bi 2i i =0 • The capacitor array interpolates the voltages between V1 and V2 . • Reference: J.-W. Yang, et al., JSSC 10/89, pp. 1458–1461. DACs 24-37 Analog ICs; Jieh-Tsorng Wu Nyquist-Rate Analog-to-Digital Converters Jieh-Tsorng Wu ES A November 13, 2002 1896 National Chiao-Tung University Department...
View Full Document

This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

Ask a homework question - tutors are online