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DACs 2424 Analog ICs; JiehTsorng Wu A Current Cell Example
Cj
SEL
Ri
R i+1 Local
Decoder Io1 CLK Io2 V1
M1 M2
Va V1 V2 SEL
V2 VB1 M3 t VSS • The current switch MOSTs, M1 and M2, are in the triode region when fully turned on.
• To minimize voltage ﬂuctuation at Va, the inverters are sized so that the crossover
voltage of the V1 and V2 transient waveforms can turn on both M1 and M2.
• Reference: CH Lin and K Bult, “A 10b, 500MSample/s CMOS DAC in 0.6 mm2,”
JSSC, 12/1998, pp. 1948–1958. DACs 2425 Analog ICs; JiehTsorng Wu ChargeRedistribution DACs
1 Vo
N1
2
C bN1 2
2C
b2 1
2C
b1 0
2C C Cp b0 Vref 1
N
2C
Vo
2 bN1 N1 2
2C C
b2 1
2C
b1 0
2C
b0 Vref
DACs 2426 Analog ICs; JiehTsorng Wu ChargeRedistribution DACs
During φ1 = 1, Vo = 0 Cap Bottom Plate @ GND
During φ2 = 1,
bi = 1
0 → Cap Bottom Plate @Vref
→ Cap Bottom Plate @GND Vo = Vref C
×
×
NC + C
2
p N −1 bi 2i
i =0 • Binaryweighted or equallyweighted capacitor array.
• Cp is top plate parasitic capacitance, and introduces a gain error.
• Opamp can be used to provide voltage gain and mitigate the eﬀects of Cp.
• DACs at resolutions of 10 bits or above usually requires some kind of trimming or
calibration. DACs 2427 Analog ICs; JiehTsorng Wu Segmented DAC Architecture
Din
N −1 N
M
MBit DAC
L
LBit DAC Di n = AM M −1 bi 2i =
i =0 bi +L2i +L + i =0 L−1 bj 2j
j =0 M −1 AL AM = ∆M × L−1 bi +L2i AL = ∆L × i =0 M −1 Ao = AM + AL = ∆L × j =0 N =M +L Ao bi +L2i +L + ∆L × i =0 ∆ M = 2L × ∆ L L−1 N −1 bj 2j = ∆L ×
j =0 bj 2j bi 2i
i =0 • The MDAC need to have ±∆L/2 accuracy.
• Signal path delay mismatch between the MDAC and the LDAC can cause glitch.
• Can have more than two segments.
DACs 2428 Analog ICs; JiehTsorng Wu A 10Bit Segmented CurrentSteering DAC
B4B6 B0B3 B4B6
Column Decoder 8x8 8x8 Row Decoder B7B9 Row Decoder Column Decoder B7B9 Io 8x8 8x8 Column Decoder B7B9 Column Decoder B4B6 DACs Row Decoder B7B9 Row Decoder Io B4B6 2429 Analog ICs; JiehTsorng Wu A 10Bit Segmented CurrentSteering DAC
• Segmented 622 architecture with commoncentroid layout.
• Each current cell in the matrix contains 4 LSB current.
• Reference: J. Bastos, et. al., “A 12Bit Intrinsic Accuracy HighSpeed CMOS DAC,”
JSSC 12/1998, pp. 1959–1969. DACs 2430 Analog ICs; JiehTsorng Wu A Segmented CurrentSteering DAC
Io VB I I VB VC I 4X VB 2X 1X 1X L M
MDAC Thermometer Decoder LDAC Binary Decoder
N
Din • Greatly reduces area for large N while ensuring monotonicity (at least for MSBs).
• The LDAC can be a binaryweighted DAC if its glitches can be tolerated.
• Reference: H. Schouwenaar, et al., JSSC 12/88, pp. 1290–1297.
DACs 2431 Analog ICs; JiehTsorng Wu DynamicallyMatched Current Sources
Out Io
Iref Calibration Switch Array Cs Cs Cs Iref Cs M1
S1 VSS
Iref IB1 Cs
VSS Out Out
Iref VB2 M3 Operation M4 Iref Cbr MC1 Cbr
M1
MS1 MS1D M1 M2 IB1 VB1 S1 Cs
VSS VSS DACs 2432 Analog ICs; JiehTsorng Wu DynamicallyMatched Current Sources
• The bias voltage for the current sources is stored in each individual Cs . The voltage
on Cs is refreshed periodically by means of calibration.
• A spare current source can be added to facilitate uninterrupted operation.
• Cs can be just the Cgs of M1.
• The switching error of MS1 as well as gm1 must be minimized.
• By adding M2 with a constant current, gm1 can be reduced.
• 16bit resolution can be achieved using this technique.
• Reference: D. Groeneveld, et al., JSSC 12/89, pp. 1517–1522. DACs 2433 Analog ICs; JiehTsorng Wu A Segmented ChargeRedistribution DAC LDAC MDAC
Vo Vx
2
2C
bj 1
2C 0
2C C
bi L Vref Vref Di n = bi 2i
i =0 DACs C M N −1 Vo = C Vref
2M M −1 ·
i =0 N =M +L Vx = Vref
2L L−1 · bj 2j
j =0 M −1
L−1
Vref
Vref N −1
1
bi +L2i +
· Vx =
·
bi +L2i +L +
bj 2j =
·
bi 2i
2M
2M + L
2N i = 0
i =0
j =0 2434 Analog ICs; JiehTsorng Wu A CapacitorResistor Hybrid DAC M
2C
MDAC
2
bi M1 2
2C C 1
2C Vo
0
2C 0
2C M Vref
LDAC
bj Vo =
DACs Vref
2M M −1 ×
i =0 L Vref Vref L−1
Vref N −1
1
bi +L2i +
×
×
bj 2j =
×
bi 2i
2M
2L
2N
j =0
i =0
2435 N =M +L Analog ICs; JiehTsorng Wu A ResistorCapacitor Hybrid DAC
1
L
2C
LDAC
2
2C L1
2
C
bj Vo
1
2C 0
2C L V2
V1 MDAC
bi M Vref M −1 V1 = ∆M × bi +L2 i V2 = V1 + ∆M i =0 DACs 2436 ∆M = Vref
2M N =M +L
Analog ICs; JiehTsorng Wu A ResistorCapacitor Hybrid DAC
During φ1 = 1, Vo = 0 Cap Bottom Plate @ GND
During φ2 = 1,
bi =
Vo = V1 + ∆M
2L L−1 × bj 2j =
j =0 1
0
Vref
2M → Cap Bottom Plate @V2
→ Cap Bottom Plate @V1
M −1 × bi +L2i +
i =0 Vref
2M + L L−1 × bj 2j =
j =0 Vref
2N N −1 × bi 2i
i =0 • The capacitor array interpolates the voltages between V1 and V2 .
• Reference: J.W. Yang, et al., JSSC 10/89, pp. 1458–1461. DACs 2437 Analog ICs; JiehTsorng Wu NyquistRate AnalogtoDigital Converters JiehTsorng Wu ES A November 13, 2002 1896 National ChiaoTung University
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.
 Winter '09
 Choma
 Integrated Circuit, Transistor, The Land

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