# Yi n2 gm2 go2 at frequencies vo 1 vs 2 go2 glcl gm2

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Unformatted text preview: ST Cascode Conﬁguration VDD VDD Telescopic Cascode Folded Cascode I1 Vo Bias V 1 V in M2 V 1 V in R S R L C v in S v g1 C C I2 L v o g gm2 = gm2 + gmb2 Multiple-T Gain Stages r gd1 r gs1 v m1 g1 Vo S g’ v m2 s2 R Bias M1 R M1 M2 o2 R L C’ R L C L L v s2 o1 C x Cx = Cd b1 + Csb2 + Cgs2 6-8 CL = CL + Cd b2 + Cgd 2 Analog ICs; Jieh-Tsorng Wu MOST Cascode Low-Frequency Characteristics The output impedance looking into M2’s drain is Rot2 = ro1 + (gm2ro1 + 1)ro2 ≈ gm2ro1ro2 The input admittance looking into M2’s source is Gi n 2 ≈ gm2 go2/GL + 1 The overall voltage gain is gm2 gm2ro1ro2 RL vo gm1 ≈− × = gm1 × ≈ gm1 × (Rot2 Av = vi n go1 + Gi n2 go2 + GL ro2 + gm2ro1 ro2 + RL • Let gm = gm1 = gm2, ro = ro1 = ro2, and gm gm gm ≈ go ≈ Gi n 2 ≈ goRL + 1 gmro + 1 Multiple-T Gain Stages 6-9 RL) 2 go. If RL = Rot2 = gmro , then gm gm 1 gm Av ≈ − ≈− 2go go + GL 2 go 2 Analog ICs; Jieh-Tsorng Wu MOST Cascode Zero-Value Time Constant Analysis Using the zero-value time constant method, we have Rgs10 = RS Rx0 = ro1 Ri n2 ≈ ro1 Rgd 10 = RS + Rx0 + gm1RS Rx0 (1/gm2 )(go2/GL + 1) RL0 = RL T0 = Rgs10 Cgs1 + Rgd 10Cgd 1 + Rx0Cx + RL0 CL Ri n2 ≈ ro Rx0 gmro ≈ 2 Rgd 10 2 ro gmroRS gmro ≈ ≈ RS + + 2 2 2 2 ⇒ T0 go. If RL = Rot2 = gmro and RS = ro, then 2 RL0 ω−3dB = 1/ gm2ro1ro2 2 • Let gm = gm1 = gm2, ro = ro1 = ro2, gm ro = 2 Rot2 ≈ RL 2 ro gmro gmro Cgd 1 + Cx + CL T0 = RS Cgs1 + 2 2 2 • RL0CL usually is the dominant term, unless RS is very large. Multiple-T Gain Stages 6-10 Analog ICs; Jieh-Tsorng Wu MOST Cascode AC Characteristics Let RL = Rot2 = gm2ro1ro2, then gm2 Gi n 2 ≈ go2RL + 1 ≈ gm2 gm2ro1 + 1 ≈ go1 The dc gain is gm2 gm1 1 gm1 gm2 × ≈− · · Av (0) ≈ − 2 go1 go2 go1 + Gi n2 go2 + GL The dominant pole is 1 2 ≈− p1 = − RL0 CL gm2ro1ro2CL At frequencies where |p1 | Av (s) = Multiple-T Gain Stages Av (0) 1− s p1 ω ≈ |p2|, Av (0) ωu gm1 ≈− =− s sCL s −p 1 6-11 gm1 ωu = Av (0) · p1 = CL Analog ICs; Jieh-Tsorng Wu MOST Cascode AC Characteristics The second pole is approximately at p2 = − go1 + Yi n2 Cx Yi n2 is the resistance looking into the M2’s source at high frequencies. Yi n2 = gm2 − go2 • At frequencies ω vo −1 vs 2 (go2 + GL)/CL, gm2 + go2 gm2 vo = ≈ vs2 go2 + GL + sCL sCL ⇒ Yi n2 ≈ gm2 go2 1− + go2 ≈ gm2 sCL gm2 gm2 ωT p2 ≈ − ≈− ≈− Cx K Cgs2 K where K is between 1 and 2 (usually closer to 1). Multiple-T Gain Stages 6-12 Analog ICs; Jieh-Tsorng Wu Active Cascode Conﬁguration Vo -g I o V bias A m2 (A+1) g v o v 2 v mb2 2 Vo i o M2 M2 g o2 M3 v 2 Vi M1 g v m1 i C2 V in g o1 M1 C2 = (A + 1)(Cgs2 + Cgd 3) + Cgs3 The M2’s transconductance is boosted as gm2 = gm2(A + 1) + gmb2, thus Rot2 = ro1 + ro2 + gm2ro1ro2 ≈ [gm2 (A + 1) + gmb2]ro1 ro2 Gi n 2 ≈ gm2(A + 1) + gmb2 go2/GL + 1 Multiple-T Gain Stages Gi n2 = gm2(A + 1) + gmb2 + go2 6-13 if RL = 0 Analog ICs; Jieh-Tsorng Wu Active Cascode Characteristics The equivalent transconductance is io Gm = vi vo =0 Gi n 2 = gm1 × = gm1 go1 + Gi n2 1− 1 1 + [gm2(A + 1) + gmb2]ro1 + ro1/ro2 • If A(s) has a dominant pole, i.e, A(s) = ao/(1 − s/p1 ) ≈ −ωu/s, ωu = ao · |p1|. The transfer function Vo/Vi has an additional zero and pole at z = −ωu p = −ωu − 1 ≈ −ωu gm2ro1ro2CL CL = Capacitor at Vo • The non-dominant pole at the M2’s source is p2 ≈ gm2 C2 = gm2(A + 1) + gmb2 (A + 1)(Cgs2 + Cgd 3) + Cgs3 gm2 ≈ Cgs2 + Cgd 3 p2 is degraded slightly by the addition of ampliﬁer A. Multiple-T Gain Stages 6-14 Analog ICs; Jieh-Tsorng Wu Super Source Follower Conﬁguration VDD g I2 C V2 Vi R = R1 = io = 0 Multiple-T Gain Stages C 2 g o1 Vo I1 vo Av (0) = vi g v m1 gs1 v gs1 Io vi =0 2 v2 C vo Ro = io R vi M2 M1 gd1 v mb1 o L C v o gs1 L g v m2 2 R ro1 + R2 [1 + (gm1 + gmb1)ro1 ](1 + gm2R2 ) gm1ro1 1 + (gm1 + gmb1)ro1 + R 2 + ro 1 R1 (1+gm2R2 ) 6-15 ≈ ≈ io 1 R L C L 1 1 gm1 + gmb1 gm2ro1 gm1ro1 1 + (gm1 + gmb1)ro1 + g 1 m2 ro 2 Analog ICs; Jieh-Tsorng Wu Diﬀerential Gain Stages Jieh-Tsorng Wu ES A July 16, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Emitter-Coupled Pair VCC Assume RC1 Vo1 Vi 1 Ic1 • Q1=Q2. RC2 Ic2 Q1 Vo2 Q2 IE E • RC1 = RC2 ≡ RC . Vi 2 • Q1 and Q2 don’t saturate. • Neglect rb, ro, and rµ. RE E • Neglect RE E , i.e, RE E → ∞. VEE Vi d ≡ Vi 1 − Vi 2 Vo1 = VCC − Ic1RC Ic1 ≈ IS 1 eVBE 1/UT Diﬀerential Gain Stages Icd ≡ Ic1 − Ic2 Vo2 = VCC − Ic2RC Ic2 ≈ IS 2 eVBE 2/UT IS 1 Vod = Vo1 − Vo2 = −(Ic1 − Ic2)RC = −Icd RC Ic1 = IS 2 ⇒ = e(VBE 1−VBE 2)/UT = eVi d /UT Ic2 7-2 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Large-Signal Behavior Summing currents at the common emitter node with αF 1 = αF 2 ≡ αF αF IE E = Ic1 + Ic2 = Ic1 1 + e Icd = Ic1 − Ic2 = αF IE E −Vi d /UT ⇒ Ic1 = − 1 1 1+ e−Vi d /UT 1+ Vod = Vo1 − Vo2 = −Icd RC = −αF IE E RC tanh Diﬀerential Gain Stages αF IE E 7-3 1+ e+Vi d /UT Vi d 2UT e−Vi d /UT Ic2 = αF IE E 1 + e+Vi d /UT = αF IE E tanh = αF IE E RC tanh Vi d 2U T −Vi d 2UT Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair with Emitter Degeneration • Series feedback used to exchange gain for linearity. • Linear input range increased by approximately same factor gain is reduced. • Doesn’t increase linear output range. Diﬀerential Gain Stages 7-4 Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair VDD I dd Assume R D1 R D2 V o1 I V o2 V I V i1 • M1=M2. SS I...
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