Analog Integrated Circuits (Jieh Tsorng Wu)

E i1 id9d10 this slew rate is sr i1 cl i1 id1

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Unformatted text preview: ises at Vx . A solution is to place both M1 and M2 in a single well, and connect well and source terminals together to eliminate body effect. • Interconnect crossovers can introduce undesired coupling capacitors to the Vi − summing node. Careful layout is required. • Fully-differential circuit topology generally has better power-supply rejection performance. Opamp-I 13-36 Analog ICs; Jieh-Tsorng Wu Device Noise Analysis VDD VDD M3 M4 v n3 V v n4 I M1 M3 I o M1 v n2 I o M2 I SS SS VSS ≈ 4kT 2 vnT Opamp-I DS3 v nT VSS 2 vn V DS3 M2 v n1 M4 Kf 1 21 · + · 3 gm W LCox f gm3 2 2 = vn 1 + vn 2 + gm1 13-37 2 in ≈ 0 2 2 2 vn 3 + vn 4 Analog ICs; Jieh-Tsorng Wu Thermal Noise Performance Assuming M1=M2 and M3=M4, and knowing ID1 = ID3 so that gm3 gm1 2 = µpCox (W/L)3 µnCox (W/L)1 = µp(W/L)3 µn (W/L)1 kn = µnCox kp = µpCox The input referred thermal noise is v(2 )T Θ gm3 41 + = 4kT gm1 3 gm1 ∆f 4 = 4kT · 3 2 × 4kT 1 41 3 gm3 × 1 + 2kn(W/L)1 ID1 = 4kT gm3 41 × 1+ gm1 3 gm1 µp (W/L)3 · µn (W/L)1 • The load contribution can be made small by making gm1 > gm3 or (W/L)1 > (W/L)3 . • gm1 should be made as large as possible to minimize thermal noise contribution. Opamp-I 13-38 Analog ICs; Jieh-Tsorng Wu Flicker Noise Performance The input referred 1/f noise is v2 (1/f )T ∆f gm3 2Kf n = + gm1 W1L1 Cox f 2Kf n 1 =× f W1L1Cox 2 µp(W/L)3 2Kf p 2Kf n = + × × W3L3Cox f W1L1Cox f µn(W/L)1 W3L3 Cox f 2Kf p Kf p µp L2 1 1+ · · Kf n µn L2 3 • Kf p is typically smaller than Kf n by a factor of two or more. • The load contribution can be made small by making L3 > L1. But longer L3 can limits the signal swing somewhat. • The width of load devices does not affect the 1/f noise performance. But make it wider can maximize signal swing. • Making W1 wider can reduce 1/f noise. Opamp-I 13-39 Analog ICs; Jieh-Tsorng Wu 2-Stage Opamp with pMOST Input Stage VDD VB1 M7 M5 Vi Vo Vi M1 Cc M2 Output Buffer V’o M6 M3 M4 VSS Opamp-I 13-40 Analog ICs; Jieh-Tsorng Wu 2-Stage Opamp with pMOST Input Stage Comparing to the nMOST-input opamps, the pMOST-input opamps have • Similar dc voltage gain. • Smaller gm1 and larger gm6. • Larger unity-gain frequency since ωu |p2| and |p2| = gm6/C2. • Better slew rate since both Vov 1 and ωu are larger. • Better 1/f noise performance. • Poorer thermal noise performance. Opamp-I 13-41 Analog ICs; Jieh-Tsorng Wu Operational Amplifiers with Single-Ended Outputs Jieh-Tsorng Wu ES A December 23, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Two-Stage Operational Amplifier with Cascode VDD M3 M4 M10 M6 • The volage gain Av ∝ (gmro)3. • Size M8 so that M4A M3A M9 Vo • Input common-mode range is reduced by cascodes. IB1 M1A M2A M8 M2 M1 VDSAT Cc VDD Vi VDS 1 = VDS 2 • The additional poles are nondominant and located near ωT . Vi VB1 M5 M7 • The 2nd stage can also use cascodes. VSS Opamp-II 14-2 Analog ICs; Jieh-Tsorng Wu Telescopic-Cascode Operational Amplifier VDD 2 • The volage gain Av ∝ (gmro) . M3 VB2 M4A M3A VDD − (VIC − Vt ) > ∆Vo + 3Vov Vo VDD ⇒ CL IB1 M1A Vi • Consider the output current branch, M4 VDD − VIC > ∆Vo + 3Vov − Vt Since VIC,mi n = Vt + 2Vov + VSS , we have M2A VDD − VSS > ∆Vo + 5Vov M8 M2 M1 • Consider the non-output branch, Vi VB1 VSS Opamp-II VDD − (VIC − Vt ) > Vt + 2Vov M5 ⇒ VDD − VIC > 2Vov 14-3 or VDD − VSS > Vt + 4Vov Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Amplifier VDD V bsp M10 M9 V ccp M4 M3 V V i+ M1 Vo M2 V ccn M6 M5 iI 1 M8 M7 C L VSS Opamp-II 14-4 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Amplifier • Consider output stage VDD − VSS > ∆Vo + 4Vov or VDD − VSS > Vt + 3Vov Consider input stage VIC,max = VDD − Vov + Vt VIC,mi n = VSS + Vt + Vov + Vo,mi n(I1) • The differential-mode voltage gain is Av = Av (0) 1 − s/p1 Av (0) = gm1Ro At midband frequencies where ω Av ≈ Opamp-II Av (0) −s/p1 p1 = − 1 RoCL Ro = 1 g o2 + g o9 g m3 ro 3 +g g o7 m5 ro 5 |p1 | = gm1 ωu = s sCL 14-5 ωu = gm1 CL Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Amplifier • The dominant poile is associated with the only high-impedance node at Vo. All other poles are located near ωT , and their magnitude are normally larger than |p2| of the two-stage opamps. • CL provides the dominant-pole frequency compensation. Increasing CL improves the phase margin. • If lead compensation is desired, a resistor can be placed in series with CL. • Use nMOST input stage for larger gm1 and better thermal noise performance. • Good PSRR since no pole-splitting Cc. • Slightly higher noise due to more devices. • Suitable for low-voltage operation. • Active cascodes can be used to increase voltage gain. Opamp-II 14-6 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Amplifier VDD V bsp M11 M12 M10 M9 V ccp M4 M3 V V i+ M1 Vo M2 V ccn M6 M5 iI 1 M8 M7 C L VSS Opamp-II 14-7 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Amplifier If bias currents ID...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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