Analog Integrated Circuits (Jieh Tsorng Wu)

E d f 1 eg 0 f dt t 2q eg0 silicon band gap at t

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Unformatted text preview: tage of VGS for strong inversion, and depends on VSB . • k = µCox is called the process transconductance. MOST 3-6 Analog ICs; Jieh-Tsorng Wu MOST I-V Characteristics ID IDSAT VDS = VDSAT Triode Region VSB = 0 Saturation (Active) Region VGS VDS Vt Vt0 ID = µCox W L 12 (VGS − Vt )VDS − VDS 2 VSB > 0 for VDS ≤ VDSAT = VGS − Vt 1 W IDSAT = ID @ VDS = VDSAT = µCox (VGS − Vt )2 2 L MOST 3-7 Analog ICs; Jieh-Tsorng Wu Threshold Voltage Vt = Vt0 + γ VSB + 2φf − 2φf for VSB > 0 Vt0 is the threshold voltage when VSB = 0. Vt0 = 2φf + γ 2φf + VF B NSUB kT ln φf = q ni γ= 2q si NSUB Cox = Cox ox tox The Fermi level φf is temperature dependent, i.e., d φf 1 Eg 0 − φf =− dT T 2q ◦ Eg0 = Silicon band gap at T = 0 K The Vt0’s temperature coefficient is 1 Eg 0 − φf =− dT T 2q d Vt0 γ 2+ 2φf ◦ ◦ • d Vt0 /d T is usually in the range between −0.5 mV/ C to −4 mV/ C. MOST 3-8 Analog ICs; Jieh-Tsorng Wu Square-Law I-V Characteristics In triode region, 1st-order long-channel model is ID = µCox W L 12 W (VGS − Vt )VDS − VDS = k 2 L 12 (VGS − Vt )VDS − VDS 2 When VDS ≥ VDSAT = VGS − Vt , the MOST is in the pinch-off region (or saturation region), 1 1W2 W IDS = IDSAT = ID (VDS = VGS − Vt ) = µCox (VGS − Vt )2 = k Vov 2 2L L • k = µCox is called the process transconductance parameter. • k = β = µCox W is called the device transconductance parameter. L • Vov = VGS − Vt is called the gate drive or the overdrive. MOST 3-9 Analog ICs; Jieh-Tsorng Wu Channel-Length Modulation ID G S D IDSAT go Leff L VDS VDSAT 1W2 ID(sat) = k V Lef f = L − ∆ 2 Lef f ov Using one-dimensional abrupt PN junction model, ∆≈ MOST 2 si qNSUB ∆VDS = VDS − VDSAT VDS − VDSAT + Ψo 3-10 Analog ICs; Jieh-Tsorng Wu Channel-Length Modulation The ID variation due to VDS can be written as: ∂Lef f ∂ID ID ∂ID 1 = × =− ×− 2 ∂VDS ∂Lef f ∂VDS Lef f 2 si qNSUB 1 VDS − VDSAT + Ψo = ID · λ The drain current in the pinch-off region can be approximated as VDS 1W2 1W2 ID(sat) = k Vov (1 + λVDS ) = k Vov 1 + 2L 2L VA • λ is inversely proportional to L, i.e., λ ∝ 1/L. −1 • Typical values of λ are in the range 0.05 V −1 to 0.005 V . • The accurate calculation of λ from the device structure is quite difficult. Extraction from experimental data is usually necessary. MOST 3-11 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Model in Saturation Region G D D G v gs B g m vgs g mb vsb go S S v sb B Transconductance = gm ≡ ∂ID W = k Vov (1 + λVDS ) = ∂VGS L 2k ID W ID (1 + λVDS ) = L Vov /2 ∂ID Output Conductance = go ≡ = λID ∂VDS MOST 3-12 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Model in Saturation Region Body Transconductance = gmb ∂Vt ∂ID ∂ID γ ≡− =− × = gm × ∂VSB ∂Vt ∂VSB 2 VSB + 2φf Thus gmb = gm × χ where χ≡ γ 2 VSB + 2φf • The factor χ is typically 0.1–0.3. • Since γ = 2q si NSUB /Cox χ = si / 2 si (VSB + 2φ f ) qNSUB 1 = Cox si /xd max Cox = Cd epl Cox xd max : The width of depletion layer under channel. Cd epl : The capacitance/area of depletion layer under channel. MOST 3-13 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Capacitances in Saturation Region Lg Gate W Source Drain C ovs C ovd C ch C cb C Body C sb L LD Csb = AS × CJ (VSB ) + P S × CJSW (VSB ) Csb = Csb + Ccb db LD Cd b = AD × CJ (VDB ) + P D × CJSW (VDB ) Ccb ≈ W L × CJ (VSB ) • AS and AD are the areas of the source/drain junctions. • P S and P D are the source/drain perimeters excluding the sides adjacent to channel. MOST 3-14 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Capacitances in Saturation Region Junction Capacitances: Csb = Csbo 1+ VSB Ψo m Cd bo Cd b = 1+ VDB Ψo m m= 11 ∼ 32 Overlap Capacitances: Covs = W × CGSO = W × (nLD Cox ) 1≤n≤2 MOST Covd = W × CGDO = W × (nLD Cox ) (Due to friniging) 3-15 Analog ICs; Jieh-Tsorng Wu Channel Capacitance in Saturation Region L QI (y ) = Cox [VGS − Vt − V (y )] = Cox [Vov − V (y )] G S dV ID = W · µQI (y ) · E (y ) = W · µQI (y ) · dy 1 W2 ID = µCox Vov 2 L D V(y) y Let VS = 0 and ID · d y = (VGS − Vt ) − V (y ) · d V µCox W 1 1 2y Integration from 0 to y ⇒ Vov = Vov V − V 2(y ) ⇒ V (y ) = Vov 2L 2 1− 1− y L L 2 2 QI (y )W d y = W LCox Vov = W LCox (VGS − Vt ) 3 3 0 ∂QT 2 Channel Capacitance = Cch ≡ = W LCox ∂VGS 3 Total Channel Charge = QT = MOST 3-16 Analog ICs; Jieh-Tsorng Wu Complete MOST Small-Signal Model in Saturation Region C G C gb C gs D gd v gs g m vgs g mb vsb go C db S C’ sb v sb B Csb MOST 2 Cgd = Covd Cgs = Covs + W LCox 3 = Csb + Ccb = (AS + W · L) × CJ (VSB ) + P S × CJSW (VSB ) 3-17 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Model in Triode Region G C gs g ds C gd S D C’ sb C’ db B ∂ID W = µCox (VGS − Vt ) for VDS → 0 ∂VDS L 1 1 Cgs = Covs + W LCox Cgd = Covd + W LCox 2 2 1 1 Csb = Csb + W LCJ (VSB ) Cd b = Cd b + W LCJ (VDB ) 2 2 gd s = MOST 3-18 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Model in Cutoff Region G C C gs C S C gb D C sb gd db B Cgs = Covs Cgd = Covd • Cgb is highly nonlinear and dependent on the gate voltage. MOST 3-19 Analog ICs; Jieh-Tsorng Wu Carrier Velocity Saturation vd gm = k gm W V L ov gm(max) vscl Vov E Ec Vov ≈ EcL...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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