Analog Integrated Circuits (Jieh Tsorng Wu)

E se is bounded for h2z 1 z as long as v stays away

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Unformatted text preview: (z ) = b1 + b2(z − 1) + b3(z − 1) + · · · D (z ) • The numerator of ST F (z ) is arbitrary, but has an order that is one less than D (z ). • The ST F (z ) does not contain significant peaking. • Each integrator output contain significant amounts of the input signal as well as filtered quantization noise. If c1 = 0 and c2 = 0, the poles of L(z ) can be moved away from z = 1 along the unit circle. Oversampling 26-25 Analog ICs; Jieh-Tsorng Wu Stability of Single-Stage High-Order Modulators Quantizer Im(z) e(k) x(k) G(z) α y(k) Re(z) F(z) αG (z ) 1 Y (z ) = · X (z ) + · E (z ) 1 + αG (z )F (z ) 1 + αG (z )F (z ) • A modulator is called stable, if the input to the quantizer does not become overloaded, i.e., e(k ) ≤ ±∆/2. • All high-order modulators (N > 2) are conditionally stable. • Modulators with multi-bit quantizer and DAC exhibit improved stability. Oversampling 26-26 Analog ICs; Jieh-Tsorng Wu Stability of Single-Stage High-Order Modulators For single-stage modulators with one-bit quantizer and DAC: • As a general rule of thumb, stability can be achieved by keeping NT F e jω ≤ 1.5. • A modulator can be made more stable by placing the poles closer to the zeros in NT F (z ). But, the SNR is also degraded since the out-of-band gain of NT F (z ) is also reduced. • Stability is also related to the input signal level. Typically want 50–80% of ∆ for stable input range. • “Signal overload” and “power on” may cause a conditionally stable modulator to oscillator. Need additional mechanism to detect instability and force the loop becoming stable. Oversampling 26-27 Analog ICs; Jieh-Tsorng Wu Multi-Stage Cascaded Modulators x(k) H 1 y (k) 1 (z) D/A Error Cancel y(k) e (k) 1 H 2 y (k) 2 (z) D/A Y1(z ) = S1(z ) · X (z ) + N1(z ) · E1(z ) Oversampling Y2(z ) = S2(z ) · E1(z ) + N2(z ) · E2(z ) 26-28 Analog ICs; Jieh-Tsorng Wu Multi-Stage Cascaded Modulators The error cancellation logic is Y (z ) = S2(z ) · Y1(z ) − N1(z ) · Y2(z ) If S2(z ) = S2(z ) and N1(z ) = N1(z ), then Y (z ) = S1(z )S2 (z ) · X (z ) − N1(z )N2 (z ) · E2(z ). • Also called multi-stage noise shaping (MASH) architecture. • Individual loop can be low-order and stable. The resulting noise shaping function N1(z )N2 (z ) · · · is high-order. • Sensitive to mismatches between the analog and digital circuitry. • For low-order loop, the finite opamp gain can cause noise leak-through. • y (k ) has more than one bit, thus complicates the output DAC design in D/A applications or the decimation filter design in A/D applications. Oversampling 26-29 Analog ICs; Jieh-Tsorng Wu A Third-Order (1-1-1) Cascaded Modulators x(k) z y (k) 1 1 z 2 z 1 y(k) D/A q 1 (k) z y (k) 2 1 z y (k) 4 2 z 1 D/A q 2 (k) z y (k) 3 1 z 1 D/A Oversampling 26-30 Analog ICs; Jieh-Tsorng Wu A Third-Order (1-1-1) Cascaded Modulators The outputs of the quantizers are Y 1 = z − 1 X + 1 − z − 1 E1 Q1 = Y1 − E1 = z −1(X − E1) Y 2 = z − 1 Q 1 + 1 − z − 1 E2 Q2 = Y2 − E2 = z −1(Q1 − E2) Y 3 = z − 1 Q 2 + 1 − z − 1 E3 = z − 2 Q 1 − z − 2 E2 + 1 − z − 1 E3 We have Y4 = z − 2 Y2 + 1 − z − 1 Y3 = z − 2 Q 1 + 1 − z − 1 2 E3 = z − 3 X − z − 3 E1 + 1 − z − 1 2 E3 and Y = z − 3 Y1 + 1 − z − 1 Y4 = z − 3 X + 1 − z − 1 Oversampling 26-31 3 E3 Analog ICs; Jieh-Tsorng Wu Idle Channel Tones (Pattern Noises) For a 1st-order 1-bit modulator and ±∆ = ±1, y (k ) = sgn[u(k )] = u(k ) + e(k ) u(k + 1) = u(k ) + x (k ) − y (k ) If x (k ) = 0 and u(0) = 0, then y (k ) = (+1, −1) · · · e(k ) = (+1, 0) · · · If x (k ) = 1/3 and u(0) = 0, then y (k ) = (+1, −1, +1) · · · e(k ) = (+1, −1/3, +1/3) · · · If x (k ) = 1/2 and u(0) = 0, then y (k ) = (+1, −1, +1, +1) · · · Oversampling e(k ) = (+1, −1/2, 0, +1/2) · · · 26-32 Analog ICs; Jieh-Tsorng Wu Idle Channel Tones (Pattern Noises) • In above examples, e is periodic and nowhere near white. Different initial states just shift the sequence and the values of e. • For bounded input |u| < 1, x is rational ⇔ y is periodic. • Low-frequency tones cannot be filtered out by the following decimation filter. • Tones also exists in higher-order modulators. The tones might not lie at a single frequency but instead be short-term periodic patterns. • Nearly all types of modulators can produce very high-powered tones near fs /2. Clock noise near this frequency can couple and demodulate these tones down into the baseband. • For ac input, strong peaks and dips in the output noise power may be seen for certain input frequencies and amplitudes. Oversampling 26-33 Analog ICs; Jieh-Tsorng Wu Noise-Shaped Dithering for Single-Stage Modulators d(k) x(k) y(k) G(z) F(z) • d (k ) is a pseudo-random noise. It is usually generated by a PN sequence generator. • The power d (k ) must be comparable to that of e(k ). The pdf of d (k ) usually spans more than ∆/2. • d (k ) may require 3–8 quantization levels for effective dithering. Oversampling 26-34 Analog ICs; Jieh-Tsor...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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