Analog Integrated Circuits (Jieh Tsorng Wu)

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Unformatted text preview: . • Store EM −2 in the data register as EM − 2 ADCs ∆CM −2 1 Dx − EM −1 = −Vref · = 2 Ctot 25-28 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs Capacitor Ci calibration, i = M − 2, M − 3, · · · CA ≡ CB = 1 2M − i 1 2M − i Ctot + ∆Ci M −1 Ctot − Vx = −Vref · ∆Cj − ∆Ci j =i +1 M −1 j =i +1 ∆Cj + 2∆Ci Ctot • Using the C-DAC to digitize Vx , we obtain Dx . • Store Ei in the data register as 1 Ei = Dx − 2 ADCs M −1 Ej = −Vref · j =i +1 25-29 ∆Ci Ctot Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs During normal operation, the Vx generated by the M-DAC is M −1 Vx = Vref 0 Ci bi +L · Ctot The Vx is corrected by the C-DAC as M −1 Vxc = Vx + M −1 (bi +L · Ei ) = Vref i =0 0 M −1 bi +L · = Vref i =0 = ADCs Vref 2M Ci bi +L · Ctot M −1 − Vref i =0 ∆Ci bi +L · Ctot Ci − ∆Ci Ctot M −1 bi +L · 2i i =0 25-30 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward (Subranging) Architectures Aj Aj+1 Gj ADC DAC da Aj ( Dj) Dj A j+1 MSBs A i Stage 1 D1 0 LSBs Stage 2 D2 Stage P DP Encoder 0 ad A (-1) ADCs Aj ad ad A (+1) A (+2) Do 25-31 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward (Subranging) Architectures The relationship between Aj and Aj +1 is Aj +1 = Aj − Ada(Dj ) j · Gj ⇒ Aj = Ada(Dj ) j + Aj +1 Gj The input Ai can be expressed as Ai = Ada 1 + Ada 2 G1 da + A3 G1 G2 da + ··· + AP G1 G2 · · · GP − 1 AP +1 + G1 G2 · · · GP da • If Aj (Dj ) and Gj are known, Ai can be computed from D1, D2, · · · , DP . • The term, Q = AP +1/(G1G2 · · · GP ), is the conversion error (quantization error). • Aad has no effect on the A/D result. j • Gj may include sample-and-hole function for pipeline or cyclic operation. ADCs 25-32 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward (Subranging) Architectures If the Gj amplifier has dc offset, i.e., Aj +1 = Aj − Ada(Dj ) j − ⇒ · Gj Aos j Aj = Ada(Dj ) j + Aos j + Aj +1 Gj The input Ai can be expressed as da Ai = Ada 1 + A2 G1 + Ada 3 da G1 G2 + ··· + AP G1 G2 · · · GP − 1 AP +1 + + Aos G1 G2 · · · GP The entire system has an dc offset of os os Aos = Aos + 1 A2 G1 + A3 G1 G2 + ··· + Aos P G1 G2 · · · GP − 1 • Ref: E. Soenen and R. Geiger, “An Architecture and An Algorithm for Fully Digital Correction of Monolithic Pipelined ADC’s,” IEEE CAS II, pp. 143–153, March 1995. ADCs 25-33 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward Minimal Design A j+1 G=2 A j+1 G=4 +1 +1 +1/2 +1/2 0 0 -1/2 Aj -1 -1/2 Aj -1 ADC DAC -1 0 ADC +1 G = G1 = G2 = · · · = GP = integer ∆A = 2 G Effective Number of Bit = N = log2 DAC Q= 1 Qmax -1 0 +1 AP +1 1 < G1 G2 · · · GP GP = P × log2 G • There are M = G − 1 comparators in the ADC. G is preferred to be power of 2. • Dj has M + 1 different values, and the DAC has corresponding M + 1 different output values. ADCs 25-34 Analog ICs; Jieh-Tsorng Wu Over-Range in the Minimal Design Assume nonideal ADC, DAC, and G, as ˆ Aad = Aad + j j ad j ˆ Ada = Ada + j j da j ˆ Gj = Gj × 1 + g j Then we have Aj +1 = Aj − Ada(Dj ) + ( j − da ) j +( ad j ad j ˆ · Gj = Aj − Ada(Dj ) · Gj + OR j The over range, OR, is OR = Aj − Ada(Dj ) j g G jj − da ) j ˆ · Gj ≤ g j +( ad j − da ) j ˆ · Gj • Nonideal ADC, DAC, and G, can cause Aj +1 in minimal design stretching over the nominal input range of the j + 1 stage. ADCs 25-35 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward Redundant Design A j+1 Minimal+2 A j+1 Minimal+1 +1 +3/4 +1/2 +1/4 0 -1/4 -1/2 Aj -1 -1 ADC 0 Aj -3/4 +1 -1 DAC ADC 0 +1 DAC • To increase the nominal input range, one can increase M , the number of comparators in the ADCs, and the corresponding output levels in the DACs. • The minimal+2 design provides an over-range capability of ±∆A. The minimal+1 design provides an over-range capability of ±∆A/2. • It is also possible to avoid the over-range phenomenon by decreasing Gj . ADCs 25-36 Analog ICs; Jieh-Tsorng Wu Digital Encoding for the Quantized-Feedforward Architecture A A2 Stage 1 i A3 Stage 2 Stage 2 D2 D1 D3 CP d G2 d G1 da Ai = Ada + 1 Table C3 C2 C1 A2 G1 + Ada 3 G1 G2 AP+1 DP Table Table Table Stage P Do da + ··· + AP G1 G2 · · · GP − 1 +Q dd d (Ai − Q) · G1 G2 · · · GP −1 d = ADCs Ada 1 G d da 1 G1 + A2 G1 d d GG d da 1 2 G2 + A3 G1 G2 25-37 dd d G1 G2 · · · GP − 1 d G3 + · · · + Ada P G G ···G 12 P −1 Analog ICs; Jieh-Tsorng Wu Digital Encoding for the Quantized-Feedforward Architecture Let Cj = Ada(Dj ) · j dd G1 G2 · · · Gjd−1 G1 G2 · · · Gj − 1 The digital output can be obtained by Do = d d d (C1) G1 + C2 G2 + · · · + CP −1 GP −1 + CP • Nonlinear A/D conversion occurs, if d ˆ Cj = Ada(Dj ) · j ADCs d d G1 G2 · · · Gj − 1 ˆ ˆˆ G1 G2 · · · Gj − 1 25-38 Analog ICs; Jieh-Tsorng Wu A Radix-2 1.5 Bit SC Pipeline Stage 2 1 Cf Conversioin Phase 1 1 Vj 0.25 Vr 0.25 Vr Vj 1 Vr x D j Encoder Vj+1 g g C C 2 Conversion Phase 2 Cf D j =...
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This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

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