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• The VOS is sampled in the sample mode, and canceled in the hold mode.
• The opamp’s output has small voltage variation. Thus, it is easier to design the opamp
for high speed.
• Suitable for high speed.
S/H 17-25 Analog ICs; Jieh-Tsorng Wu A MOST Recycling S/H
Sample Mode Vi Vo M2 M1 φ1 B1 Vi Hold Mode Vo Vo B2
B1 a C φ1
H1 B1 M3
C H2 C H1 C C H2 H1 C H2 M4
1 A1 M5
a φ1 H3
CLK φ1 φa
φ1 φ2 φ2
S/H a φ2
17-26 Analog ICs; Jieh-Tsorng Wu A MOST Recycling S/H
• B1 and B2 are two unity-gain buﬀer.
• M5 and CH 3 is to compensate for the M4’s switching error.
• The switching errors of M1 and M2 does not aﬀect Vo.
• The switching error of M3 does aﬀect Vo. But its eﬀect is reduced by the opamp’s
• Mismatch between B1 and B2 can aﬀect Vo. S/H 17-27 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H φ Vi A1 1
C S/H 17-28 Vo H Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H
• The circuit is in the track mode when φ = 1, and is in the hold mode when φ = 0.
• High input impedance.
• The oﬀset and gain of the output buﬀer are not critical.
• The input oﬀset of the A1 opamp is not canceled.
• The speed can be seriously degraded due to the necessity of guaranteeing that the
loop is stable in the track mode.
• The A1 opamp is open loop when in the hold mode. It takes time to recover the bias
when switches to the track mode. S/H 17-29 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H with Improved tslew
φ φ M3
Vi A1 M3 φ 1
C Vo H • During hold mode, A1 is conﬁgured as a unity-gain ampliﬁer. Thus, the slewing time
is greatly minimized.
S/H 17-30 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H Using Active Integrator C φ Vi A1 M1 φ S/H M3 φ 17-31 H1 A2
M2 C Vo H2 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H Using Active Integrator
• When in the track mode, the voltage on both sides of M1 are closed to ground, and
are nearly signal independent.
• Aperture jitter is minimized.
• The switching error of M1 causes a dc oﬀset in Vo, which will be signal independent.
• M2 and CH 2 are to compensate for the M1 switching error.
• When in the hold mode, M3 clamps the A1’s output to ground, speeding up the time
it takes the S/H to return to the tack mode.
• M3 also reduces signal feedthrough when in the hold mode.
• The speed is degraded because of the necessity to guarantee stability in the track
S/H 17-32 Analog ICs; Jieh-Tsorng Wu An RC Closed-Loop S/H R
φ C H R
φ A1 Vo M2 • The A1 opamp need to have low output impedance. S/H 17-33 Analog ICs; Jieh-Tsorng Wu A Switched-Capacitor Closed-Loop S/H
Vi φ2 M1 M4
C a C φ2 H1 φ1 = 1 Sample Mode C H1 H3
M3 C H2 φa
C M6 C C
H2 H4 H4 φ2 = 1 Hold Mode C φ1 C
H1 φ2 H3 A1 a A2 φ1 C a φ2 S/H Vo A2 A1 a φ1 H3 17-34 Vo H2 Analog ICs; Jieh-Tsorng Wu A Switched-Capacitor Closed-Loop S/H
• The Vo is always valid.
• The VOS 1 of A1 is stored in CH 2 during the sample mode.
• The M2’s switching error is canceled by M3.
• The M5’s switching error is canceled by M6.
• The switching error of M1 and M4 doesn’t aﬀect Vo. S/H 17-35 Analog ICs; Jieh-Tsorng Wu Charge Redistribution Sampled-Data Ampliﬁer
C Q C 2 C 2 2 a
S3 V 1
i V S1
S2 V o V i V
V OS OS φ1 = 1 a φ1 V1
o C V o 1
V OS φ2 = 1 φ1
t1 S/H t2 17-36 Analog ICs; Jieh-Tsorng Wu Charge Redistribution Sampled-Data Ampliﬁer
To consider the ideal case, let A = ∞ and VOS = 0, then
Vo(t1) = 0
C1Vi (t1) = C2Vo(t2) ⇒ C1
× Vi (t1)
C2 To consider the VOS eﬀect, let A = ∞, then
Vo(t1) = VOS (t1)
× VOS (t2) − VOS (t1)
× Vi (t1) + VOS (t1) + 1 +
× VOS (t2) − VOS (t1)
× Vi (t1) +
· VOS (t1) + 1 +
• The input referred oﬀset is VOS · (C2 /C1).
S/H 17-37 Analog ICs; Jieh-Tsorng Wu Charge Redistribution Sampled-Data Ampliﬁer
To consider the ﬁnite gain eﬀect, let VOS = 0, then during φ2 = 1
C1 Vi + C1 V1 = C2(Vo − V1) Vo = −AV1 ⇒ Vo = C1
C2 1 + 1 1 + C1
2 To consider the eﬀect S3 switching error, let A = ∞, VOS = 0, and Vi = 0, then during
φ2 = 1
Vo = VOS = −
• VOS is independent of input.
• If S3 is opened before S1, the switching errors of S1 and S2 have no eﬀect on Vo. S/H 17-38 Analog ICs; Jieh-Tsorng Wu Charge Redistribution Summing Ampliﬁer
C 3 During the sample mode (φ1 = 1)
V V V V 1
2 i2 Vo = VOS S5
C o 1 S2 V C1
(V − Vi 2)
C3 i 1 OS 1
2 i4 S/H C During the hold mode (φ2 = 1) C2
+ (Vi 3 − Vi 4) + VOS
C3 2 S4 17-39 Analog ICs; Jieh-Tsorng Wu Sampled-Data Ampliﬁer with CDS
C 2 a2
1 C 1 C 2 2 S5
i V S1
S2 V o V
V OS OS φ1 = 1 a φ1 o V V1
i C V o 1
V OS φ2 = 1 φ1
S/H t2 17-40 Analog ICs; Jieh-Tsorng Wu Sampled-Data Ampliﬁer with CDS
Let A = ∞, then
Vo(t1) = Vc1 = Vc2 = VOS (t1)
Vo(t2) = − C1
[VOS (t2) − VOS (t1)]
× Vi (t2) + 1 +
C2 • The correlated double-sampling (CDS) technique, resulting in VOS (nTs ) − VOS (nTs −
Ts /2), can reduce the e...
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