Analog Integrated Circuits (Jieh Tsorng Wu)

Transconductance is gmcs i2 vi c d m go5 1 szt 2

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 4 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation with Feedforward Transconductors C c2 C c1 Fbk Vi gm1 R1 v1 gm2 C1 R2 v2 gm3 C2 R3 v3 Vo C3 gmf2 gmf1 2 a(s) = − Feedback R3(n0 + n1s + n2s ) 1 + b1s + b2s2 + b3s3 12-45 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation with Feedforward Transconductors b1 = b1 + gmf 2R1R3 Cc2 b2 = b2 + gmf 2R1R2 R3(C2 + Cc1)Cc2 b3 = b3 n0 = −gm1gm2gm3R1 R2 − gmf 1 − gm1gmf 2R1 n1 = gm1(gm2 − gmf 2)R1R2Cc1 + (gm1 − gmf 1)R1Cc2 − gmf 1R2(C2 + Cc1 ) − gmf 1R1C1 − gm1gmf 2R1R2C2 n2 = (gm1 − gmf 1)R1R2(C2 + Cc1)Cc2 − gmf 1R1R2(C2 + Cc1 )C1 • To eliminate zeros, one can set n1 = n2 = 0. • If gmf 1 = gm1 and gmf 2 = gm2, then n0, n1, and n2 are all negative, and both zeros are in the LHP. • With gmf 1 = gm1 and gmf 2 = gm2, b1 ≈ a1 and the dominant pole p1 is not changed by gmf . However, p2 and p3 will be different from the case without gmf 1 and gmf 2. Feedback 12-46 Analog ICs; Jieh-Tsorng Wu Basic Two-Stage Operational Amplifier Design Jieh-Tsorng Wu ES A December 23, 2002 1896 National Chiao-Tung University Department of Electronics Engineering Ideal Operational Amplifier Single-Ended Output Vi Fully Differential Vi Vo Vo A/2 x Vi AxV i Vcm A/2 x Vi Vi Vi Vo • Vo = A × Vi • Ideal opamp: – A → ∞, Zi n → ∞, Zout → 0. – No frequency dependence. Opamp-I 13-2 Analog ICs; Jieh-Tsorng Wu Basic 2-Stage CMOS Opamp VDD M3 M4 M6 Vi M1 M2 Vo Cc Output Buffer V’o 1 V’o Vi VB1 M5 M7 VSS Vi Vi Cc A1 Differential Input Stage Opamp-I A2 Second Gain Stage 13-3 Vo Optional Output Buffer Analog ICs; Jieh-Tsorng Wu Constant gm Bias Generator VDD M14 M13 M3 W L M4 W L M6 Vi M1 Cc M2 W L Vo Vi VB1 M12 M5 R VSS 2µCox (W/L)ID gm3,m4 = gm11 · Opamp-I 1 = 3 = 13 W L 2 W L 4 W L 14 =α· 12 W L 11 VSS B gm = W L M7 M11 = √ 2 α−1 gm11 = √ RB α µp (W/L)3 µn (W/L)11 1 (W/L)5 2 (W/L)11 13-4 (W/L)1 gm1,m2 = gm11 · gm6 = gm11 · (W/L)11 1 (W/L)5 2 (W/L)11 µp (W/L)6 (W/L)7 µn (W/L)11 (W/L)11 Analog ICs; Jieh-Tsorng Wu Input Stage Small-Signal Model gm3 go3 gm4 vy VDD M3 M4 Vo1 Vi M1 M2 go4 Cy vy io1 vo1 vo1 Vi C1 go1 VB1 io1 go2 Gm vx R1 C1 M5 VSS gm1 = gm2 gm1 ( vi1 vx ) gm3 = gm4 Cx go5 go1 = go2 gm2 ( vi2 vx ) go3 = go4 gm go Cy ≈ Cgs3 + Cgs4 = 2Cgs3 Opamp-I 13-5 Analog ICs; Jieh-Tsorng Wu Input Stage Output Impedance gm3 go3 gm4 vy Cy go4 vy It2 go1 vt go5 it2 ≈ vt · go2 go2 Cx it1 = vt · go4 f →∞ it3 ≈ i1 ≈ 0 G1 = go2 + go4 vx gm1 ( vi1 vx ) G1 = 1/R1 = vt /it it = it1 + it2 + it3 it It1 I1 vi 1 = vi 2 = 0 It3 f →0 gm2 ( vi2 vx ) it2 ≈ vt · go2/2 it3 ≈ i1 ≈ it2 G1 = go2 + go4 go2(gm1 + go5 + sCx ) go2 1 + sCx /gm1 it2 · = ≈ vt 2 1 + sCx /(2g ) gm2 + gmb2 + go2 + gm1 + go5 + sCx m1 gm1 = gm1 + gmb1 Opamp-I Cx = Cx + Cgs1 + Cgs2 13-6 Analog ICs; Jieh-Tsorng Wu Input Stage Differential-Mode Transconductance gm3 go3 gm4 vy Cy 1 1 vi d = vi 2 − vi 1 vi 1 = − vi d vi 1 = + vi d 2 2 1 i1 = gm1vi 1 = − gm1vi d 2 1 i2 = gm2vi 2 = + gm1vi d 2 gm3 gm4 −i4 = ≈ i1 gm3 + go1 + go3 + sCy gm3 + sCy i4 go4 vy io1 vo1 go1 i1 go2 i2 vx gm1 ( vi1 vx ) gm2 ( vi2 vx ) io = −i4 − i2 gm3 io 1 Gmd (s) ≡ = − gm1 1 + vi d 2 gm3 + sCy zm = Mirror Zero = − Opamp-I 2gm3 Cy = −gm1 · ≈ −ωt3 13-7 1 + sCy /(2gm3) 1 + sCy /gm3 = −gm1 · pm = Mirror Pole = − gm3 Cy ≈− 1 − s/zm 1 − s/pm ωt3 2 Analog ICs; Jieh-Tsorng Wu Input Stage Common-Mode Transconductance gm3 go3 gm4 vy Cy I4 go4 vy vi c = vi 1 = vi 2 io1 I2 I1 go1 vo1 Cx m) io1 = −i4 − i2 = i1(1 − ⇒ io1 = −i2( go5 d) −i4 = i1(1 − go2 vx gm1 ( vi1 vx ) i1 = i2(1 − gm2 ( vi2 vx ) Gmc d + m − d m) io1 i2 = ≈− ·( vi c vi c m) − i2 ≈ −i2 ( d + d + m) m) gm1(go5 + sCx ) go5 + sCx go5 1 − s/zt gm1 i2 · = = ≈ = vi c 1 + 2(gm1+gmb1) 2(gm1 + gmb1) + go5 + sCx 2 + sCx /gm1 2 1 − s/pt (g +sC ) o5 x zt = Tail Zero = − Opamp-I go5 Cx 2gm1 pt = Tail Pole = − Cx 13-8 Analog ICs; Jieh-Tsorng Wu Input Stage Common-Mode Transconductance For the M1-M2 source-coupled pair, i1 = gm1(vi c − vx ) + go1(vy − vx ) i2 = gm2(vi c − vx ) + go2(0 − vx ) = gm1(vi c − vx ) − go1vx i1 vy = − gm3 + go3 + sCy We have i1 = i2 + go1vy = i2 − i1 · i1 = i2 d Opamp-I 1 1+ g o1 gm3 +go3+sCy ≈ i2 go1 gm3 + go3 + sCy go1 1− gm3 + go3 + sCy = i2(1 − d) go1 go1 go1 go1 1 1 = ≈ = · = · gm3 + go3 + sCy gm3 + sCy gm3 1 + sCy /gm3 gm3 1 − s/pm 13-9 Analog ICs; Jieh-Tsorng Wu Input Stage Common-Mode Transconductance For the M3-M4 current mirror, go3 + sCy gm3 gm4 i4 = =1− =1− −= i1 gm3 + go3 + sCy gm3 + go3 + sCy gm3 + go3 + sCy go3 1 + sCy /go3 go3 1 + sCy /go3 = ≈ = · = · gm3 + go3 + sCy gm3 + sCy gm3 1 + sCy /gm3 gm3 1 − s/pm go3 + sCy m m go3 + sCy The common-mode transconductance is Gmc(s) ≈ − i2 ·( vi c d + m) go5 1 − s/zt · · ≈− 2 1 − s/pt go3 1 + sCy /go3 go1 1 · + · gm3 1 − s/pm gm3 1 − s/pm go5(go1 + go3) (1 − s/zt )(1 − s/zc ) · =− 2gm3 (1 − s/pt )(1 − s/pm) Opamp-I 13-10 zc = − go1 + go3 Cy Analog ICs; Jieh-Tsorng Wu Input Stage Voltage Gain A dm ω A cm ω Ad m = Gd m · Z1 1 1 1 Z1 = = · G1 + sC1 go2 + go4 1 − s/po go2 + go4 po = Output Load Pole...
View Full Document

This note was uploaded on 03/26/2013 for the course EE 260 taught by Professor Choma during the Winter '09 term at USC.

Ask a homework question - tutors are online