CECS341-Fall2020-Lecture 3-MIPS ISA and Assembly Language.pdf

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CECS 341: Computer Architecture & Organization Hossein Sayadi, PhD Department of Computer Engineering & Computer Science California State University, Long Beach Fall 2020
MIPS ISA and Assembly Language 2
Lecture Outline The MIPS Instruction Set Architecture Review of the MIPS architecture characteristics MIPS Assembly Language Instructions Arithmetic and Logical Load and Store Branch, Jump, and Conditional Hennessey/Patterson: A.10, 2.1 2.7 3
MIPS Instruction Set The MIPS is a RISC architecture. Contains a set of simple instructions. Instructions in the Core Instruction Set are classified as Arithmetic Data Transfer Logical Conditional Branch Unconditional Jump Other instructions are available for floating point operations. Implemented by the co-processor. 4
MIPS Register Set Consists of thirty-two 32-bit registers. Most are general-purpose registers. Some have special purposes. $zero = contains the value 0. $sp = Stack Pointer $fp = Frame Pointer $ra = Return Address Register others. Registers are identified by Name in Assembly Language Number in Machine Language
MIPS Addressing Modes 6
Overview of MIPS Datapath 7
MIPS Instruction Formats The MIPS has three instruction formats. Design Principle : Good design requires good compromise. Ideally, all instructions conform to a single instruction format. Leads to simpler instruction decoding and simpler decode logic. Results in more efficient execution of program instructions. More instruction formats offer greater flexibility. Leads to a greater variety of instructions. Results in an instruction set that provides more functionality. The formats are similar. They have common fields, which simplifies instruction decoding. The MIPS has fixed-length instructions. All instructions are 32-bits long. 8
MIPS Instruction Formats 9 31 26 25 21 20 16 15 11 10 6 5 0 opcode Rs Rt Rd shamt funct R-type destination register in R-type instructions specified in bits 15 .. 11 All MIPS machine language instructions are 32-bits long. Uses three register operands R-type format is used by all arithmetic and logical instructions Rs (source) register specified in bits 25 .. 21 for R-type and I-type instructions
MIPS Instruction Formats 10 31 26 25 21 20 16 15 0 opcode Rs Rt immediate I-type Rs (source) register specified in bits 25 .. 21 for R- type and I-type instructions destination register in I-type instructions specified in bits 20 .. 16 All MIPS machine language instructions are 32-bits long. Uses two register operands and an address/immediate value I-type format is used by load and store instructions I-type format is used by arithmetic and logical instructions with a constant
MIPS Instruction Formats 11 31 26 25 0 opcode address J-type opcode specified in bits 31 .. 26 for all instructions All MIPS machine language instructions are 32-bits long.

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