0x7ffffc 0x000000 0xfffffe 0x800002 0x800000 decimal

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Unformatted text preview: 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 DS22192D-page 28 2011 Microchip Technology Inc. MCP3901 TABLE 5-6: OSR = 64 OUTPUT CODE EXAMPLES ADC Output code (MSB First) 0 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Hexadecimal 0x7FFFF0 0x7FFFE0 0x000000 0xFFFFF0 0x800010 0x800000 Decimal 20-Bit Resolution + 524, 287 + 524, 286 0 -1 - 524,287 - 524, 288 TABLE 5-7: OSR = 32 OUTPUT CODE EXAMPLES ADC Output code (MSB First) Hexadecimal 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7FFF80 0x7FFF00 0x000000 0xFFFF80 0x800080 0x800000 Decimal 17-Bit Resolution + 65, 535 + 65, 534 0 -1 - 65,535 - 65, 536 0 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 5.7 5.7.1 Voltage Reference INTERNAL VOLTAGE REFERENCE The MCP3901 contains an internal voltage reference source, specially designed to minimize drift over temperature. In order to enable the internal voltage reference, the VREFEXT bit in the Configuration register must be set to `0' (Default mode). This internal VREF supplies reference voltage to both channels. The typical value of this voltage reference is 2.37V 2%. The internal reference has a very low typical temperature coefficient of 12 ppm/C, allowing the output codes to have minimal variation with respect to temperature, since they are proportional to (1/VREF). The noise of the internal voltage reference is low enough not to significantly degrade the SNR of the ADC if compared to a precision, external low noise voltage reference. The output pin for the internal voltage reference is REFIN+/OUT. When the internal voltage reference is enabled, the REFIN- pin should always be connected to AGND. For optimal ADC accuracy, appropriate bypass capacitors should be placed between REFIN+/OUT and AGND. Decoupling at the sampling frequency, around 1 MHz, is important for any noise around this frequency will be aliased back into the conversion data (0.1 F ceramic and 10 F tantalum capacitors are recommended). These bypass capacitors are not mandatory for correct ADC operation, but removing these capacitors may degrade the accuracy of the ADC. The bypass capacitors also help the applications where the voltage reference output is connected to other circuits. In this case, additional buffering may be needed as the output drive capability of this output is low. 5.7.2 DIFFERENTIAL EXTERNAL VOLTAGE INPUTS When the VREFEXT bit is high, the two reference pins (REFIN+/OUT, REFIN-) become a differential voltage reference input. The voltage at the REFIN+/OUT pin is noted as VREF+ and the voltage at the REFIN- pin is noted as VREF-. The differential voltage input value is given by the following equation: EQUATION 5-4: VREF = VREF+ VREFThe specified VREF range is from 2.2V to 2.6V. The REFIN- pin voltage (VREF-) should be limited to 0.3V. Typically, for single-ended reference applications, the REFIN- pin should be directly connected to AGND. 2011 Microchip Technology Inc. DS22192D-page 29 MCP3901 5.8 Power-on Reset 5.9 The MCP3901 contains an internal POR circuit that monitors analog supply voltage AVDD during operation. The typical threshold for a power-up event detection is 4.2V 5%. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 F ceramic and 10 F tantalum) should be mounted as close as possible to the AVDD pin, providing additional transient immunity. Figure 5-4 illustrates the different conditions at power-up and a power-down event in the typical conditions. All internal DC biases are not settled until at least 50 s after system POR. Any DR pulses during this time, after a system Reset, should be ignored. After POR, DR pulses are present at the pin with all the default conditions in the Configuration registers. Both AVDD and DVDD power supplies are independent. Since AVDD is the only power supply that is monitored, it is highly recommended to power up DVDD first as a power-up sequence. If AVDD is powered up first, it is highly recommended to keep the RESET pin low during the whole power-up sequence. RESET Effect on Delta-Sigma Modulator/SINC Filter When the RESET pin is low, both ADCs will be in Reset and output code, 0x0000h. The RESET pin performs a Hard Reset (DC biases still on, part ready to convert) and clears all charges contained in the Delta-Sigma modulators. The comparators' output is `0011' for each ADC. The SINC filters are all reset, as well as their double output buffers. This pin is independent of the serial interface. It brings the CONFIG registers to the default state. When RESET is low, any write with the SPI interface will be disabled and will have no effect. All output pins (SDO, DR, MDAT0/1) are high...
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