Unformatted text preview: -Noise and distortion ratio are similar to the Signal-to-Noise ratio, with the exception that you must include the harmonics power in the noise power calculation. The SINAD specification mainly depends on the OSR and DITHER settings. 4.12 Spurious-Free Dynamic Range (SFDR) EQUATION 4-5: SINAD EQUATION SFDR is the ratio between the output power of the fundamental and the highest spur in the frequency spectrum. The spur frequency is not necessarily a harmonic of the fundamental, even though it is usually the case. This figure represents the dynamic range of the ADC when a full-scale signal is used at the input. This specification depends mainly on the DITHER setting. SignalPower SINAD ( dB ) = 10 log -------------------------------------------------------------------- Noise + HarmonicsPower The calculated combination of SNR and THD per the following formula also yields SINAD: EQUATION 4-9:
FundamentalPower SFDR ( dB ) = 10 log ---------------------------------------------------- HighestSpurPower- EQUATION 4-6: SINAD, THD AND SNR RELATIONSHIP SNR --------- 10 SINAD ( dB ) = 10 log 10 + 10 THD -------------- 10 2011 Microchip Technology Inc. DS22192D-page 21 MCP3901
4.13 MCP3901 Delta-Sigma Architecture
These Idle tones are residues that are inherent to the quantization process and the fact that the converter is integrating at all times without being reset. They are residues of the finite resolution of the conversion process. They are very difficult to attenuate and they are heavily signal dependent. They can degrade both the SFDR and THD of the converter, even for DC inputs. They can be localized in the baseband of the converter, and thus, difficult to filter from the actual input signal. For power metering applications, Idle tones can be very disturbing because energy can be detected even at the 50 or 60 Hz frequency, depending on the DC offset of the ADCs, while no power is really present at the inputs. The only practical way to suppress or attenuate the Idle tones phenomenon is to apply dithering to the ADC. The Idle tone amplitudes are a function of the order of the modulator, the OSR and the number of levels in the quantizer of the modulator. A higher order, a higher OSR or a higher number of levels for the quantizer will attenuate the Idle tones amplitude. The MCP3901 incorporates two Delta-Sigma ADCs with a multi-bit architecture. A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator, which is digitizing the quantity of charge integrated by the modulator loop (see Figure 5-1). The quantizer is the block that is performing the Analog-to-Digital conversion. The quantizer is typically 1 bit, or a simple comparator which helps to maintain the linearity performance of the ADC (the DAC structure, is in this case, inherently linear). Multi-bit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the OSR, which leads to better SNR figures. Typically, however, the linearity of such architectures is more difficult to achieve, since the DAC is no more simple to realize, and its linearity limits the THD of such ADCs. The MCP3901's 5-level quantizer is a Flash ADC, composed of 4 comparators arranged with equally spaced thresholds and a thermometer coding. The MCP3901 also includes proprietary 5-level DAC architecture that is inherently linear for improved THD figures. 4.15 Dithering 4.14 Idle Tones A Delta-Sigma Converter is an integrating converter. It also has a finite quantization step (LSB) which can be detected by its quantizer. A DC input voltage that is below the quantization step should only provide an all zeros result, since the input is not large enough to be detected. As an integrating device, any Delta-Sigma will show, in this case, Idle tones. This means that the output will have spurs in the frequency content that are depending on the ratio between quantization step voltage and the input voltage. These spurs are the result of the integrated sub-quantization step inputs that will eventually cross the quantization steps after a long enough integration. This will induce an AC frequency at the output of the ADC and can be shown in the ADC output spectrum. In order to suppress or attenuate the Idle tones present in any Delta-Sigma ADCs, dithering can be applied to the ADC. Dithering is the process of adding an error to the ADC feedback loop in order to "decorrelate" the outputs and "break" the Idle tones behavior. Usually, a random or pseudo-random generator adds an analog or digital error to the feedback loop of the Delta-Sigma ADC in order to ensure that no tonal behavior can happen at its outputs. This error is filtered by the feedback loop, and typically, has a zero average value so that the converter static transfer function is not disturbed by the dithering process. However, the dithering process slightly increases the noise floor (it adds noise to the part) while reducing its...
View Full Document
This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13