2 19 03 10 26 29 03 pf v v v vref vref

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Unformatted text preview: CALE) VREF VREF+ VREF-- 2.2 1.9 -0.3 -- -- -- -- 10 2.6 2.9 0.3 pF V V V VREF = (VREF+ VREF-), VREFEXT = 1 VREFEXT = 1 VREF TCREF ZOUTREF -2% -- -- 2.37 12 7 +2% -- -- V VREFEXT = 0 Symbol Min Typical Max Units Conditions ppm/C VREFEXT = 0 k AVDD = 5V, VREFEXT = 0 2: 3: 4: 5: 6: 7: 8: This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the maximum signal range, VIN = -0.5 dBFS @ 50/60 Hz = 353 mVRMS, VREF = 2.4V. See terminology section for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11, VREFEXT = 1, CLKEXT = 1. Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values). Outside of this range, the ADC accuracy is not specified. An extended input range of 6V can be applied continuously to the part with no risk for damage. For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz, AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to `0'. 2011 Microchip Technology Inc. DS22192D-page 3 MCP3901 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5V; -40C < TA < +85C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS = 333 mVRMS @ 50/60 Hz Parameters Output Data Rate Symbol fD Min Typical See Table 4-2 Max Units ksps Conditions fD = DRCLK = DMCLK/ OSR = MCLK/ (4 x PRESCALE x OSR) All analog input channels, measured to AGND (Note 7) (Note 4) -40C < TA < 125C (Note 1) (Note 6) From -40C to +125C G=1 All Gains GAIN = 1, DITHER = On Proportional to 1/AMCLK OSR = 256, DITHER = On OSR = 256, DITHER = On OSR = 256, DITHER = On OSR = 256, DITHER = On OSR = 256, DITHER = On Analog Input Absolute Voltage on CH0+, CH0-, CH1+, CH1- Pins Analog Input Leakage Current CHn+ -1 -- +1 V AIN -- -- -- -3 -- -- -2.5 -- 1 2 -- -- 3 -0.4 -- 1 15 -- 91 79 -104 -85 91 81 109 87 -133 -- -- 500/GAIN +3 -- -- +2.5 -- -- -- -- -- -102 -84 -- -- -- -- -- nA nA mV mV V/C % % ppm k dB dB dB dB dB dB dB dB dB Differential Input Voltage Range (CHn+ CHn-) Offset Error (Note 2) Offset Error Drift Gain Error (Note 2) Gain Error Drift Integral Nonlinearity (Note 2) Input Impedance Signal-to-Noise and Distortion Ratio (Notes 2, 3) Total Harmonic Distortion (Notes 2, 3) Signal-to-Noise Ratio (Notes 2, 3) Spurious Free Dynamic Range (Note 2) Crosstalk (50/60 Hz) (Note 2) Note 1: INL ZIN SINAD GE VOS ppm/C From -40C to +125C -- 350 89 78 THD -- -- SNR 89 80 SFDR -- -- CTALK -- 2: 3: 4: 5: 6: 7: 8: This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the maximum signal range, VIN = -0.5 dBFS @ 50/60 Hz = 353 mVRMS, VREF = 2.4V. See terminology section for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11, VREFEXT = 1, CLKEXT = 1. Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values). Outside of this range, the ADC accuracy is not specified. An extended input range of 6V can be applied continuously to the part with no risk for damage. For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz, AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to `0'. DS22192D-page 4 2011 Microchip Technology Inc. MCP3901 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5V; -40C < TA < +85C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS = 333 mVRMS @ 50/60 Hz Parameters AC Power Supply Rejection DC Power Supply Rejection DC Common-Mode Rejection Ratio (Note 2) Oscillator Input Master Clock Frequency Range Power Specifications Operating Voltage, Analog Operating Voltage, Digital Power On Reset Threshold AVDD DVDD POR 4.5 2.7 -- -- Operating Current, Analog (Note 4) AIDD -- -- -- -- Operating Current, Digital DIDD -- -- -- Shutdown Current, Analog Shutdown Current, Digital Note 1: IDDS,A IDD...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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