Unformatted text preview: active-low pulse with a period that is equal to the DRCLK clock period, and with a width equal to one DMCLK period. When not active-low, this pin can either be in highimpedance (when DR_HIZN = 0) or in a defined logic high state (when DR_HIZN = 1). This is controlled through the Configuration registers. This allows multiple devices to share the same data ready pin (with a pull-up resistor connected between DR and DVDD) in 3-phase, energy meter designs to reduce pin count. A single device on the bus does not require a pull-up resistor. After a data ready pulse has occurred, the ADC output data can be read through SPI communication. Two sets of latches at the output of the ADC prevent the communication from outputting corrupted data (see Section 6.10 "Data Ready Latches and Data Ready Modes (DRMODE<1:0>)"). The CS pin has no effect on the DR pin, which means even if CS is high, data ready pulses will be provided (except when the configuration prevents them from outputting data ready pulses). The DR pin can be used as an interrupt when connected to an MCU or DSP. While the RESET pin is low, the DR pin is not active. Data Ready Latches and Data Ready Modes (DRMODE<1:0>) To ensure that both channels' ADC data is present at the same time for SPI read, regardless of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the `read start' triggers. The first set of latches holds each output when the data is ready and latches both outputs together when DRMODE<1:0> = 00. When this mode is on, both ADCs work together and produce one set of available data after each data ready pulse (that corresponds to the lagging ADC data ready). The second set of latches ensures that when reading starts on an ADC output, the corresponding data is latched so that no data corruption can occur. If an ADC read has started, in order to read the following ADC output, the current reading needs to be completed (all bits must be read from the ADC Output Data registers). 6.10.1 DATA READY PIN (DR) CONTROL USING DRMODE BITS There are four modes that control the data ready pulses and these modes are set with the DRMODE<1:0> bits in the STATUS/COM register. For power metering applications, DRMODE<1:0> = 00 is recommended (Default mode). DS22192D-page 38 2011 Microchip Technology Inc. MCP3901
The position of the DR pulses vary, with respect to this mode, to the OSR and to the PHASE settings: DRMODE<1:0> = 11: Both data ready pulses from ADC Channel 0 and ADC Channel 1 are output on the DR pin. DRMODE<1:0> = 10: Data ready pulses from ADC Channel 1 are output on the DR pin. The DR from ADC Channel 0 is not present on the pin. DRMODE<1:0> = 01: Data ready pulses from ADC Channel 0 are output on the DR pin. The DR from ADC Channel 1 is not present on the pin. DRMODE<1:0> = 00 (Recommended and Default mode): Data ready pulses from the lagging ADC between the two are output on the DR pin. The lagging ADC depends on the PHASE register and on the OSR. In this mode, the two ADCs are linked together so their data is latched together when the lagging ADC output is ready. 6.10.2 DR PULSES WITH SHUTDOWN OR RESET CONDITIONS There will be no DR pulses if DRMODE<1:0> = 00 when either one or both of the ADCs are in Reset or shutdown. In Mode 0,0, a DR pulse only happens when both ADCs are ready. Any DR pulse will correspond to one data on both ADCs. The two ADCs are linked together and act as if there was only one channel with the combined data of both ADCs. This mode is very practical when both ADC channels' data retrieval and processing need to be synchronized, as in power metering applications. Note: If DRMODE<1:0> = 11, the user will still be able to retrieve the DR pulse for the ADC not in shutdown or Reset (i.e., only 1 ADC channel needs to be awake). Figure 6-8 represents the behavior of the data ready pin with the different DRMODE and DR_LTY configurations, while shutdown or Resets are applied. 2011 Microchip Technology Inc. DS22192D-page 39 3*DRCLK period DRCLK Period 1 DMCLK Period DRCLK Period Internal reset synchronisation (1 DMCLK period) 3*DRCLK period DRCLK period RESET RESET<0> or SHUTDOWN<0> RESET<1> or SHUTDOWN<1> DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 PHASE > 0 DRMODE=01; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 PHASE = 0 DRMODE=01; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 PHASE < 0 DRMODE=01; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 MCP3901 D14 D15 D16 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 Data Ready Behavior. D29 D30 D31 D32 D33 D34 DRMODE=00: Select the lagging Data Ready DRMODE=01: Select the Data Ready on channel 0 DRMODE=10: Select the Data Rea...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13