4 this is the fastest clock present in the device

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Unformatted text preview: output data rate (i.e., the rate at which the ADCs output new data). Each new data is signaled by a Data Ready pulse on the DR pin. This data rate is depending on the OSR and the prescaler with the following formula: EQUATION 4-3: DMCLK AMCLK MCLK DRCLK = --------------------- = --------------------- = ---------------------------------------------------------OSR 4 OSR 4 OSR PRESCALE 2011 Microchip Technology Inc. DS22192D-page 19 MCP3901 Since this is the output data rate, and since the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. The following table describes the various combinations of OSR and PRESCALE, and their associated AMCLK, DMCLK and DRCLK rates. TABLE 4-2: PRE <1:0> 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Note: 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE OSR <1:0> 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 OSR 256 128 64 32 256 128 64 32 256 128 64 32 256 128 64 32 AMCLK MCLK/8 MCLK/8 MCLK/8 MCLK/8 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK MCLK MCLK MCLK DMCLK MCLK/32 MCLK/32 MCLK/32 MCLK/32 MCLK/16 MCLK/16 MCLK/16 MCLK/16 MCLK/8 MCLK/8 MCLK/8 MCLK/8 MCLK/4 MCLK/4 MCLK/4 MCLK/4 DRCLK MCLK/8192 MCLK/4096 MCLK/2048 MCLK/1024 MCLK/4096 MCLK/2048 MCLK/1024 MCLK/512 MCLK/2048 MCLK/1024 MCLK/512 MCLK/256 MCLK/1024 MCLK/512 MCLK/256 MCLK/128 DRCLK (ksps) 0.4882 0.976 1.95 3.9 0.976 1.95 3.9 7.8125 1.95 3.9 7.8125 15.625 3.9 7.8125 15.625 31.25 SINAD (dB) 91.4 86.6 78.7 68.2 91.4 86.6 78.7 68.2 91.4 86.6 78.7 68.2 91.4 86.6 78.7 68.2 ENOB (bits) 14.89 14.10 12.78 11.04 14.89 14.10 12.78 11.04 14.89 14.10 12.78 11.04 14.89 14.10 12.78 11.04 For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1. 4.5 Oversampling Ratio (OSR) 4.6 Offset Error The ratio of the sampling frequency to the output data rate is OSR = DMCLK/DRCLK. The default OSR is 64 or with MCLK = 4 MHz and PRESCALE = 1, AMCLK = 4 MHz, fS = 1 MHz, fD = 15.625 ksps. The following bits in the CONFIG1 register are used to change the Oversampling Ratio (OSR). TABLE 4-3: CONFIG OSR<1:0> 0 0 1 1 0 1 0 1 MCP3901 OVERSAMPLING RATIO SETTINGS OVERSAMPLING RATIO OSR 32 64 (default) 128 256 This is the error induced by the ADC when the inputs are shorted together (VIN = 0V). The specification incorporates both PGA and ADC offset contributions. This error varies with PGA and OSR settings. The offset is different on each channel and varies from chip to chip. This offset error can easily be calibrated out by a MCU with a subtraction. The offset is specified in mV. The offset on the MCP3901 has a low temperature coefficient; see Section 2.0 "Typical Performance Curves". 4.7 Gain Error This is the error induced by the ADC on the slope of the transfer function. It is the deviation expressed in percent (%) compared to the ideal transfer function defined by Equation 5-3. The specification incorporates both PGA and ADC gain error contributions, but not the VREF contribution (it is measured with an external VREF). This error varies with PGA and OSR settings. The gain error on the MCP3901 has a low temperature coefficient; see the typical performance curves for more information, Figure 2-24 and Figure 2-25. DS22192D-page 20 2011 Microchip Technology Inc. MCP3901 4.8 Integral Nonlinearity Error 4.11 Total Harmonic Distortion (THD) Integral nonlinearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. It is the maximum remaining error after calibration of offset and gain errors for a DC input signal. The total harmonic distortion is the ratio of the output harmonic's power to the fundamental signal power for a sinewave input and is defined by Equation 4-7: EQUATION 4-7: HarmonicsPower THD ( dB ) = 10 log ---------------------------------------------------- FundamentalPower The THD calculation includes the first 35 harmonics for the MCP3901 specifications. The THD is usually only measured with respect to the 10 first harmonics. THD is sometimes expressed in %. For converting the THD in %, here is the formula: 4.9 Signal-to-Noise Ratio (SNR) For the MCP3901 ADC, the Signal-to-Noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal), when the input is a sinewave at a predetermined frequency. It is measured in dB. Usually, only the maximum Signal-to-Noise ratio is specified. The SNR calculation mainly depends on the OSR and DITHER settings of the device. EQUATION 4-8: THD ( % ) = 100 10 THD ( dB ) -----------------------20 EQUATION 4-4: SIGNAL-TO-NOISE RATIO SignalPower SNR ( dB ) = 10 log --------------------------------- NoisePower 4.10 Signal-to-Noise Ratio And Distortion (SINAD) This specification depends mainly on the DITHER setting. The most important figure of merit, for the analog performance of the ADCs present on the MCP3901, is the Signal-to-Noise and Distortion (SINAD) specification. Signal-to...
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