Unformatted text preview: 2011 Microchip Technology Inc. DS22192D-page 35 MCP3901
6.7 Continuous Communication, Looping on Address Sets
The STATUS/COM register contains the loop settings for the internal address counter (READ<1:0>). The internal address counter can either stay constant (READ<1:0> = 00) and continuously read the same byte, or it can auto-increment and loop through the register groups defined below (READ<1:0> = 01), register types (READ<1:0> = 10) or the entire register map (READ<1:0> = 11). Each channel is configured independently as either a 16-bit or 24-bit data word, depending on the setting of the corresponding WIDTH bit in the CONFIG1 register. For continuous reading, in the case of WIDTH = 0 (16-bit), the lower byte of the ADC data is not accessed and the part jumps automatically to the following address (the user does not have to clock out the lower byte since it becomes undefined for WIDTH = 0). Figure 6-6 represents a typical, continuous read communication with the default settings (DRMODE<1:0> = 00, READ<1:0> = 10) for both WIDTH settings. This configuration is typically used for power metering applications. If the user wishes to read back either of the ADC channels continuously, or both channels continuously, the internal address counter of the MCP3901 can be set to loop on specific register sets. In this case, there is only one control byte on SDI to start the communication. The part stays within the same loop until CS returns high. This internal address counter allows the following functionality: Read one ADC channel's data continuously Read both ADC channel's data continuously (both ADC data can be independent or linked with DRMODE settings) Continuously read the entire register map Continuously read each separate register Continuously read all Configuration registers Write all Configuration registers in one communication (see Figure 6-7) CS SCK SDI CH0 ADC ADDR/R SDO CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte DR These bytes are not present when WIDTH=0 (16-bit mode) FIGURE 6-6: Typical Continuous Read Communication. DS22192D-page 36 2011 Microchip Technology Inc. MCP3901
6.7.1 CONTINUOUS WRITE
The following register sets are defined as types: Both ADCs are powered up with their default configurations, and begin to output DR pulses immediately (RESET<1:0> and SHUTDOWN<1:0> bits are off by default). The default output codes for both ADCs are all zeros. The default modulator output for both ADCs is `0011' (corresponding to a theoretical zero voltage at the inputs). The default phase is zero between the two channels. It is recommended to enter into ADC Reset mode for both ADCs, just after power-up, because the desired MCP3901 register configuration may not be the default one, and in this case, the ADC would output undesired data. Within the ADC Reset mode (RESET<1:0> = 11), the user can configure the whole part with a single communication. The write commands automatically increment the address so that the user can start writing the PHASE register and finish with the CONFIG2 register in only one communication (see Figure 6-7). The RESET<1:0> bits are in the CONFIG2 register to allow exiting the Soft Reset mode, and have the whole part configured and ready to run in only one command. The following register sets are defined as groups: TABLE 6-2:
Type ADC DATA (both channels) REGISTER TYPES
Addresses 0x00-0x05 0x06-0x0B CONFIGURATION 6.8 Situations that Reset ADC Data Immediately after the following actions, the ADCs are temporarily reset in order to provide proper operation: 1. 2. 3. 4. 5. Change in PHASE register. Change in the OSR setting. Change in the PRESCALE setting. Overwrite of the same PHASE register value. Change in the CLKEXT bit in the CONFIG2 register, modifying internal oscillator state. TABLE 6-1:
Group ADC DATA CH0 ADC DATA CH1 REGISTER GROUPS
Addresses 0x00-0x02 0x03-0x05 0x06-0x08 0x09-0x0B After these temporary Resets, the ADCs go back to the normal operation with no need for an additional command. These are also the settings where the DR position is affected. The PHASE register can be used to serially Soft Reset the ADCs, without using the RESET bits in the Configuration register, if the same value is written in the PHASE register. MOD, PHASE, GAIN CONFIG, STATUS AVDD CS SCK SDI 00011000 11XXXXXX CONFIG2 00001110 PHASE ADDR/W xxxxxxxx PHASE xxxxxxxx GAIN xxxxxxxx STATUS/COM xxxxxxxx CONFIG1 xxxxxxxx CONFIG2 CONFIG2 ADDR/W Optional Reset of Both ADCs One Command for Writing Complete Configuration FIGURE 6-7: Recommended Configuration Sequence at Power-up. 2011 Microchip Technology Inc. DS22192D-page 37 MCP3901
6.9 Data Ready Pin (DR) 6.10
To signify when channel data is ready for transmission, the data ready signal is available on the Data Ready pin (DR) through an active-low pulse at the end of a channel conversion. The data ready pin outputs an...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13