Dr d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14

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Unformatted text preview: dy on channel 1 DRMODE=11: Select both Data ready Data Ready pulse that appears only when DR_LTY=0 DS22192D-page 40 FIGURE 6-8: 2011 Microchip Technology Inc. MCP3901 7.0 INTERNAL REGISTERS The addresses associated with the internal registers are listed below. A detailed description of the registers follows. All registers are 8-bit long and can be addressed separately. Read modes define the groups and types of registers for continuous read communication or looping on address sets. . TABLE 7-1: Address 0x00 0x03 0x06 0x07 0x08 0x09 0x0A 0x0B REGISTER MAP Name DATA_CH0 DATA_CH1 MOD PHASE GAIN STATUS/COM CONFIG1 CONFIG2 Bits 24 24 8 8 8 8 8 8 R/W R R Description Channel 0 ADC Data <23:0>, MSB First Channel 1 ADC Data <23:0>, MSB First R/W Delta-Sigma Modulators Output Register R/W Phase Delay Configuration Register R/W Gain Configuration Register R/W Status/Communication Register R/W Configuration Register 1 R/W Configuration Register 2 TABLE 7-2: REGISTER MAP GROUPING FOR CONTINUOUS READ MODES READ<1:0> Address = 01 = 10 = 11 GROUP 0x00 Function 0x02 0x03 DATA_CH1 MOD PHASE GAIN STATUS/ COM CONFIG1 CONFIG2 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 2011 Microchip Technology Inc. GROUP LOOP ENTIRE REGISTER MAP DATA_CH0 0x01 GROUP GROUP TYPE TYPE DS22192D-page 41 MCP3901 7.1 ADC Channel Data Output Registers ADC read communication occurs. When a data ready event occurs during a read communication, the most current ADC data is also latched to avoid data corruption issues. The three bytes of each channel are updated synchronously at a DRCLK rate. The three bytes can be accessed separately, if needed, but are refreshed synchronously. The ADC Channel Data Output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with READ<1:0> bits). These registers are latched when an REGISTER 7-1: R-0 DATA_CHn <23> bit 23 R-0 DATA_CHn <15> bit 15 R-0 DATA_CHn <7> bit 7 Legend: R = Readable bit -n = Value at POR bit 23-0 CHANNEL OUTPUT REGISTERS: ADDRESS 0x00-0x02: CH0; 0x03-0x05; CH1 R-0 R-0 DATA_CHn <21> R-0 DATA_CHn <20> R-0 DATA_CHn <19> R-0 DATA_CHn <18> R-0 DATA_CHn <17> R-0 DATA_CHn <16> bit 16 R-0 R-0 DATA_CHn <13> R-0 DATA_CHn <12> R-0 DATA_CHn <11> R-0 DATA_CHn <10> R-0 DATA_CHn <9> R-0 DATA_CHn <8> bit 8 R-0 R-0 DATA_CHn <5> R-0 DATA_CHn <4> R-0 DATA_CHn <3> R-0 DATA_CHn <2> R-0 DATA_CHn <1> R-0 DATA_CHn <0> bit 0 DATA_CHn <22> DATA_CHn <14> DATA_CHn <6> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DATA_CHn<23:0> DS22192D-page 42 2011 Microchip Technology Inc. MCP3901 7.2 Modulator Output Register The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input of 0V on both ADCs. Each bit in this register corresponds to one comparator output on one of the channels. . This register should be used as a read-only register. (Note 1). This register is updated at the refresh rate of DMCLK (typically, 1 MHz with MCLK = 4 MHz). See Section 5.4 "Modulator Output Block" for more details. REGISTER 7-2: R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3-0 Note 1: MODULATOR OUTPUT REGISTER (MOD): ADDRESS 0x06 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 bit 0 COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown COMPn_CH1: Comparator Outputs from Channel 1 Modulator bits COMPn_CH0: Comparator Outputs from Channel 0 Modulator bits This register can be written in order to overwrite modulator output data, but any writing here will corrupt the ADC_DATA on the next three data ready pulses. 2011 Microchip Technology Inc. DS22192D-page 43 MCP3901 7.3 PHASE Register 7.3.1 PHASE RESOLUTION FROM OSR The PHASE register (PHASE<7:0>) is a 7 bits + sign, MSB first, two's complement register that indicates how much phase delay there should be between Channel 0 and Channel 1. The reference channel for the delay is Channel 1, which typically, is the voltage channel when used in energy metering applications (i.e., when PHASE register code is positive, Channel 0 is lagging Channel 1). When PHASE register code is negative, Channel 0 is leading versus Channel 1. The delay is given by the following formula: The timing resolution of the phase delay is 1/DMCLK, or 1 s, in the default configuration (MCLK = 4 MHz). The PHASE register coding depends on the OSR setting: OSR = 256: The delay can go from -128 to +127. PHASE<7> is the sign bit. Phase<6> is the MSB and PHASE<0> the LSB. OSR = 128: The delay can go from -64 to +63. PHASE<6> is the sign bit. Phase<5> is the MSB and PHASE<0&g...
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